{"id":77936,"date":"2019-08-22T14:46:05","date_gmt":"2019-08-22T14:46:05","guid":{"rendered":"https:\/\/\/cerebras-met-1200-milliards-de-transistors-sur-une-puce-ia\/"},"modified":"2019-08-22T14:46:05","modified_gmt":"2019-08-22T14:46:05","slug":"cerebras-met-1200-milliards-de-transistors-sur-une-puce-ia","status":"publish","type":"post","link":"https:\/\/www.ecinews.fr\/fr\/cerebras-met-1200-milliards-de-transistors-sur-une-puce-ia\/","title":{"rendered":"Cerebras met 1200 milliards de transistors sur une puce IA"},"content":{"rendered":"

Mesurant 46 225 mm2 et optimis\u00e9 pour l\u2019intelligence artificielle, le moteur Cerebras Wafer Scale Engine (WSE) est 56,7 fois plus grand que la plus grande unit\u00e9 de traitement graphique qui mesure 815 mm2, et il contient 1200 milliards de transistors. La puce WSE, ajoute la soci\u00e9t\u00e9, offre \u00e9galement 3 000 fois plus de m\u00e9moire haute vitesse sur puce et 10 000 fois plus de bande passante m\u00e9moire.<\/span><\/p>\n

\u00ab\u00a0Con\u00e7u d\u00e8s le d\u00e9part pour l’IA, le Cerebras WSE contient des innovations fondamentales qui font \u00e9voluer les technologies de pointe en r\u00e9solvant des d\u00e9fis techniques vieux de plusieurs d\u00e9cennies qui limitaient la taille des puces – telles que la connectivit\u00e9 interne, le rendement en fabrication, la fourniture de puissance, et la mise en bo\u00eetier \u00ab\u00a0, explique Andrew Feldman, fondateur et PDG de Cerebras Systems. \u00ab\u00a0Toutes les d\u00e9cisions architecturales ont \u00e9t\u00e9 prises pour optimiser les performances du travail en intelligence artificielle. Le r\u00e9sultat est que le Cerebras WSE offre, en fonction de la charge de travail, des centaines, voire des milliers de fois les performances des solutions existantes pour une fraction infime de la consommation et de l’encombrement.\u00a0\u00bb<\/span><\/p>\n

En mati\u00e8re d\u2019intelligence artificielle, la taille des puces rev\u00eat une importance capitale, car les puces plus larges sont en mesure de traiter les informations plus rapidement et donc de fournir des r\u00e9ponses plus rapidement. La r\u00e9duction du temps n\u00e9cessaire \u00e0 la compr\u00e9hension, ou \u00ab\u00a0temps d’aprentissage\u00a0\u00bb – un obstacle majeur aux progr\u00e8s de l\u2019ensemble du secteur – permet aux chercheurs de tester plus d\u2019id\u00e9es, d\u2019utiliser plus de donn\u00e9es et de r\u00e9soudre de nouveaux probl\u00e8mes.<\/span><\/p>\n

Les gains de performances de la puce sont obtenus en acc\u00e9l\u00e9rant tous les \u00e9l\u00e9ments de l’aprentissage des r\u00e9seaux de neurones. Un r\u00e9seau de neurones est une boucle de r\u00e9troaction informatique \u00e0 plusieurs niveaux. Plus les entr\u00e9es sont rapides dans la boucle, plus la boucle apprend ou \u00ab\u00a0s’entra\u00eene\u00a0\u00bb rapidement. La solution pour d\u00e9placer les entr\u00e9es dans la boucle plus rapidement consiste \u00e0 acc\u00e9l\u00e9rer le calcul et la communication au sein de la boucle.<\/span><\/p>\n

Avec 56,7 fois plus de surface de silicium que la plus grande unit\u00e9 de traitement graphique, le WSE fournit plus de c\u0153urs pour effectuer les calculs et plus de m\u00e9moire au plus pr\u00e8s des c\u0153urs pour que les c\u0153urs puissent fonctionner efficacement. Comme cette vaste grille de c\u0153urs et de m\u00e9moire sont int\u00e9gr\u00e9s sur une seule puce, toutes les communications sont maintenues sur la puce, offrant ainsi une bande passante exceptionnelle qui permet aux groupes de c\u0153urs de collaborer avec une efficacit\u00e9 maximale. La bande passante m\u00e9moire n’est plus un goulot d’\u00e9tranglement.<\/span><\/p>\n

La Cerebras WSE h\u00e9berge 400 000 c\u0153urs de calcul optimis\u00e9s pour l’IA, sans cache, sans surcharge, et 18 gigaoctets de m\u00e9moire SRAM locale, distribu\u00e9e et ultra-rapide, constituant le seul et unique niveau de la hi\u00e9rarchie de la m\u00e9moire. La bande passante m\u00e9moire est de 9 p\u00e9taoctets par seconde. Les c\u0153urs sont reli\u00e9s entre eux par un r\u00e9seau de communication maill\u00e9, \u00e0 la pointe de la technologie, enti\u00e8rement \u00ab\u00a0cabl\u00e9\u00a0\u00bb, qui fournit une bande passante globale de 100 p\u00e9tabits par seconde. Plus de c\u0153urs, plus de m\u00e9moire locale et une structure \u00e0 large bande passante et \u00e0 faible temps de latence cr\u00e9ent l\u2019architecture optimale pour acc\u00e9l\u00e9rer le travail de l\u2019IA, explique la soci\u00e9t\u00e9.<\/p>\n

La WSE est fabriqu\u00e9e par TSMC sur sa technologie de fabrication avanc\u00e9e \u00e0 16 nm.<\/span><\/p>\n

A lire \u00e9galement:<\/p>\n

Nvidia lance un module IA \u00e0 $99 offrant 472 GFLOPS<\/a><\/strong><\/p>\n

Nvidia rach\u00e8te Mellanox pour $6.9 milliards<\/a><\/strong><\/p>\n

Super-ordinateur europ\u00e9en bas\u00e9 sur des modules ATOS<\/a><\/strong><\/p>\n

Premi\u00e8re IP de v\u00e9rification pour PCI Express 5.0<\/a><\/strong><\/p>\n

Cerebras Systems<\/a><\/p>\n

 <\/p>\n

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La startup Cerebras Systems sp\u00e9cialiste de l’acc\u00e9l\u00e9ration du calcul AI (Los Altos, Californie) a d\u00e9voil\u00e9 ce qu’il dit \u00eatre la plus grande puce jamais construite, comprenant plus de 1 200 milliards de transistors.<\/p>\n","protected":false},"author":22,"featured_media":77937,"comment_status":"closed","ping_status":"closed","sticky":false,"template":"","format":"standard","meta":{"_acf_changed":false,"footnotes":""},"categories":[883],"tags":[920,912,896,905,906,908,890,917],"domains":[47],"ppma_author":[1149],"class_list":["post-77936","post","type-post","status-publish","format-standard","has-post-thumbnail","hentry","category-technologies","tag-artificialintelligence-fr","tag-dataacquisition-fr","tag-digitalsignalprocessing-fr","tag-memory-data-storage-fr","tag-mpus-mcus-fr","tag-plds-fpgas-asics-fr","tag-powermanagement-fr","tag-software-embedded-tools-fr","domains-electronique-eci"],"acf":[],"yoast_head":"Cerebras met 1200 milliards de transistors sur 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