{"id":77736,"date":"2019-08-26T22:00:14","date_gmt":"2019-08-26T22:00:14","guid":{"rendered":"https:\/\/\/record-du-monde-pour-un-fpga-de-plus-de-9-millions-de-cellules\/"},"modified":"2019-08-26T22:00:14","modified_gmt":"2019-08-26T22:00:14","slug":"record-du-monde-pour-un-fpga-de-plus-de-9-millions-de-cellules","status":"publish","type":"post","link":"https:\/\/www.ecinews.fr\/fr\/record-du-monde-pour-un-fpga-de-plus-de-9-millions-de-cellules\/","title":{"rendered":"Record du monde pour un FPGA de plus de 9 millions de cellules"},"content":{"rendered":"<p><span class=\"tlid-translation translation\" lang=\"fr\">Avec 35 milliards de transistors, le VU19P fournit la densit\u00e9 logique et le nombre d&rsquo;entr\u00e9es \/ sorties le plus \u00e9lev\u00e9 sur un seul composant jamais construit, permettant ainsi l&rsquo;\u00e9mulation et le prototypage des technologies ASIC et SoC les plus avanc\u00e9es de demain, ainsi que de tester des applications dans les domaines des mesures, des calculs, des r\u00e9seaux, de l&rsquo;a\u00e9rospatiale et des technologies de l&rsquo;information et des applications li\u00e9es \u00e0 la d\u00e9fense.<\/span><\/p>\n<p><span class=\"tlid-translation translation\" lang=\"fr\">Avec 9 millions de cellules logiques syst\u00e8me, jusqu&rsquo;\u00e0 1,5 terabits par seconde de bande passante m\u00e9moire DDR4 et jusqu&rsquo;\u00e0 4,5 terabits par seconde de bande passante \u00e9metteur-r\u00e9cepteur et plus de 2 000 E \/ S utilisateur, le nouveau FPGA permet le prototypage et l&rsquo;\u00e9mulation des SoC les plus complexes d&rsquo;aujourd&rsquo;hui ainsi que le d\u00e9veloppement d&rsquo;algorithmes complexes \u00e9mergents tels que ceux utilis\u00e9s pour l&rsquo;intelligence artificielle, l&rsquo;apprentissage automatique, le traitement vid\u00e9o et la fusion de capteurs. Le VU19P est 1,6 fois plus grand que son pr\u00e9d\u00e9cesseur et qil \u00e9tait auparavant le plus grand FPGA du secteur &#8211; le FPGA 20 nm Virtex UltraScale.<\/span><\/p>\n<p><span class=\"tlid-translation translation\" lang=\"fr\">\u00abLe VU19P permet aux d\u00e9veloppeurs d\u2019acc\u00e9l\u00e9rer la validation du mat\u00e9riel et de commencer l\u2019int\u00e9gration logicielle avant que leur ASIC ou leur SoC ne soit disponible\u00bb, a d\u00e9clar\u00e9 Sumit Shah, directrice principale, Marketing et gestion de la ligne de produits, Xilinx. \u201cIl s&rsquo;agit de notre troisi\u00e8me g\u00e9n\u00e9ration de FPGA records. Premi\u00e8rement, le Virtex-7 2000T, suivi du Virtex UltraScale VU440, et maintenant du Virtex UltraScale + VU19P. Mais ceci est plus que la technologie du silicium; nous fournissons des flux d\u2019outils robustes et \u00e9prouv\u00e9s ainsi que l\u2019IP pour le prendre en charge. \u00ab\u00a0<\/span><\/p>\n<p><span class=\"tlid-translation translation\" lang=\"fr\">Le VU19P s&rsquo;appuie sur un ensemble complet d&rsquo;outils de d\u00e9bogage, de visibilit\u00e9 et IP, offrant aux clients une plate-forme de d\u00e9veloppement compl\u00e8te pour la conception et la validation rapides d&rsquo;applications et de technologies de nouvelle g\u00e9n\u00e9ration. La co-validation mat\u00e9rielle et logicielle permet aux d\u00e9veloppeurs de cr\u00e9er des logiciels et d&rsquo;impl\u00e9menter des fonctionnalit\u00e9s personnalis\u00e9es avant que des pi\u00e8ces physiques ne soient disponibles. De plus, le flux de conception peut \u00eatre co-optimis\u00e9 en utilisant Xilinx Vivado\u00ae Design Suite, qui permet de r\u00e9duire les co\u00fbts et les risques en fabrication, ainsi que d\u2019am\u00e9liorer l\u2019efficacit\u00e9 et le d\u00e9lai de mise sur le march\u00e9. Le VU19P sera disponible \u00e0 l&rsquo;automne 2020.<\/span><\/p>\n<p>\u00e0 lire \u00e9galement:<\/p>\n<p><a href=\"https:\/\/www.electronique-eci.com\/news\/les-fpgas-ont-des-defauts-de-securite-inherents\">Les FPGAs ont des d\u00e9fauts de s\u00e9curit\u00e9 inh\u00e9rents<\/a><\/p>\n<p><a href=\"https:\/\/www.electronique-eci.com\/news\/hardwarebee-permet-aux-ingenieurs-de-faire-le-meilleur-choix-entre-fpga-ou-asic\">Hardwarebee permet aux ing\u00e9nieurs de faire le meilleur choix entre FPGA ou ASIC<\/a><\/p>\n<p><a href=\"https:\/\/www.electronique-eci.com\/news\/fpga-soc-architecture-risc-v\">FPGA SoC \u00e0 architecture RISC-V <\/a><\/p>\n<p><a href=\"https:\/\/www.electronique-eci.com\/news\/intel-va-racheter-easic-le-pionnier-des-asic-structures\">Intel va racheter eASIC le pionnier des ASIC structur\u00e9s <\/a><\/p>\n<p>Xilinx &#8211; <a href=\"http:\/\/www.xilinx.com\/\" target=\"_blank\" rel=\"noopener\">www.xilinx.com<\/a><\/p>\n<p>&nbsp;<\/p>\n","protected":false},"excerpt":{"rendered":"<p>Xilinx a \u00e9largi sa famille de composants Virtex UltraScale + 16 nm avec le  le Virtex UltraScale + VU19P qui serait plus grand FPGA du monde,.<\/p>\n","protected":false},"author":22,"featured_media":77737,"comment_status":"closed","ping_status":"closed","sticky":false,"template":"","format":"standard","meta":{"_acf_changed":false,"footnotes":""},"categories":[883],"tags":[920,908],"domains":[47],"ppma_author":[1149],"class_list":["post-77736","post","type-post","status-publish","format-standard","has-post-thumbnail","hentry","category-technologies","tag-artificialintelligence-fr","tag-plds-fpgas-asics-fr","domains-electronique-eci"],"acf":[],"yoast_head":"<title>Record du monde pour un FPGA de plus de 9 millions de cellules ...<\/title>\n<meta name=\"description\" content=\"Xilinx a \u00e9largi sa famille de composants Virtex UltraScale + 16 nm avec le  le Virtex UltraScale + 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