{"id":70024,"date":"2019-11-25T01:31:44","date_gmt":"2019-11-25T01:31:44","guid":{"rendered":"https:\/\/\/ip-phy-de-connectivite-puce-a-puce\/"},"modified":"2019-11-25T01:31:44","modified_gmt":"2019-11-25T01:31:44","slug":"ip-phy-de-connectivite-puce-a-puce","status":"publish","type":"post","link":"https:\/\/www.ecinews.fr\/fr\/ip-phy-de-connectivite-puce-a-puce\/","title":{"rendered":"IP PHY de connectivit\u00e9 puce \u00e0 puce"},"content":{"rendered":"

Cette nouvelle IP PHY puce-\u00e0-puce est une technologie critique destin\u00e9e aux micro-puces et aux syst\u00e8mes en bo\u00eetier, qui permet aux fabricants de syst\u00e8mes sur puce de proposer des solutions davantage personnalis\u00e9es qui allient des performances et des rendements plus \u00e9lev\u00e9s, tout en raccourcissant les cycles de d\u00e9veloppement et en abaissant les co\u00fbts gr\u00e2ce \u00e0 une r\u00e9utilisation plus efficace d\u2019IP.
\nLe nouveau bloc IP puce-\u00e0-puce sur couche physique UltraLink fonctionne \u00e0 un d\u00e9bit nominal pouvant atteindre 40 Gbits\/s sur une interface s\u00e9rie NRZ (Non-Return-to-Zero), assurant une bande passante unidirectionnelle de 1 Tbit\/s par mm. Les fonctions de correction d\u2019alignement (built-in de-skew) et de brouillage\/d\u00e9sembrouillage embarqu\u00e9es facilite l\u2019int\u00e9gration des syst\u00e8mes. Alors que les solutions existantes requi\u00e8rent au moins 30 % de fils en plus, le nombre limit\u00e9 de fils \u2014 \u00e0 savoir 28 pour une bande passante de 1 Tbit\/s, simplifie le routage et abaisse potentiellement le co\u00fbt du conditionnement mise en boitier. De plus, contrairement \u00e0 certaines solutions puce-\u00e0-puce moins v\u00e9loces qui n\u00e9cessitent un interposeur silicium pour obtenir une bande passante identique, l\u2019IP puce-\u00e0-puce sur couche PHY UltraLink apporte des avantages de co\u00fbt significatifs gr\u00e2ce \u00e0 la prise en charge de modules multi-puces (MMC) sur substrats organiques. Enfin, cette IP pr\u00e9sente un temps de latence aller-retour de seulement 5 ns entre le r\u00e9cepteur et l\u2019\u00e9metteur, utilise en standard un codage NRZ (non-return-to-zero), et se caract\u00e9rise par un taux d\u2019erreurs binaire (BER) meilleur que 10-15 sans correction d\u2019erreur anticip\u00e9e (FEC \u2014 Forward Error Correction). Enfin, le bloc IP UltraLink est \u00e9prouv\u00e9 sur silicium en technologie avanc\u00e9e 7 nm FinFET.<\/p>\n

www.cadence.com\/go\/ultralink<\/a><\/p>\n

Cadence annonce la certification de son flot complet d\u2019outils pour les technologies N6 et N5P de TSMC<\/a><\/h3>\n

Bizen, plus rapide, plus petit, moins gourmand que le CMOS<\/a><\/h3>\n

Celsius Thermal Solver, premier solveur de cosimulation \u00e9lectrique-thermique complet pour l\u2019analyse au niveau syst\u00e8me<\/a><\/h3>\n","protected":false},"excerpt":{"rendered":"

Cadence annonce sa nouvelle IP PHY de connectivit\u00e9 puce \u00e0 puce UltraLink D2D pour les applications de hautes performances avec un conditionnement peu on\u00e9reux. Cette interface de haute performance \u00e0 faible temps de latence et \u00e9prouv\u00e9e sur le silicium enrichit le portefeuille d\u2019IP de calcul haute performance (HPC) propos\u00e9 par Cadence pour les secteurs de l\u2019intelligence artificielle et de l\u2019apprentissage automatique, de la 5G, du cloud computing et des r\u00e9seaux.<\/p>\n","protected":false},"author":9,"featured_media":70025,"comment_status":"closed","ping_status":"closed","sticky":false,"template":"","format":"standard","meta":{"_acf_changed":false,"footnotes":""},"categories":[881],"tags":[],"domains":[47],"ppma_author":[1141],"class_list":["post-70024","post","type-post","status-publish","format-standard","has-post-thumbnail","hentry","category-nouveaux-produits","domains-electronique-eci"],"acf":[],"yoast_head":"IP PHY de connectivit\u00e9 puce \u00e0 puce ...<\/title>\n<meta name=\"description\" content=\"Cadence annonce sa nouvelle IP PHY de connectivit\u00e9 puce \u00e0 puce UltraLink D2D pour les applications de hautes performances avec un conditionnement peu...\" \/>\n<meta name=\"robots\" content=\"index, follow, max-snippet:-1, max-image-preview:large, max-video-preview:-1\" \/>\n<link rel=\"canonical\" href=\"https:\/\/www.ecinews.fr\/fr\/wp-json\/wp\/v2\/posts\/70024\/\" \/>\n<meta property=\"og:locale\" content=\"fr_FR\" \/>\n<meta property=\"og:type\" content=\"article\" \/>\n<meta property=\"og:title\" content=\"IP PHY de connectivit\u00e9 puce \u00e0 puce\" \/>\n<meta property=\"og:description\" content=\"Cadence annonce sa nouvelle IP PHY de connectivit\u00e9 puce \u00e0 puce UltraLink D2D pour les applications de hautes performances avec un conditionnement peu on\u00e9reux. Cette interface de haute performance \u00e0 faible temps de latence et \u00e9prouv\u00e9e sur le silicium enrichit le portefeuille d\u2019IP de calcul haute performance (HPC) propos\u00e9 par Cadence pour les secteurs de l\u2019intelligence artificielle et de l\u2019apprentissage automatique, de la 5G, du cloud computing et des r\u00e9seaux.\" \/>\n<meta property=\"og:url\" content=\"https:\/\/www.ecinews.fr\/fr\/wp-json\/wp\/v2\/posts\/70024\/\" \/>\n<meta property=\"og:site_name\" content=\"EENewsEurope\" \/>\n<meta property=\"article:published_time\" content=\"2019-11-25T01:31:44+00:00\" \/>\n<meta property=\"og:image\" content=\"https:\/\/cdn.eenewseurope.com\/wp-content\/uploads\/import\/default\/files\/sites\/default\/files\/images\/eci8284_cadence.jpg\" \/>\n\t<meta property=\"og:image:width\" content=\"1097\" \/>\n\t<meta property=\"og:image:height\" content=\"602\" \/>\n\t<meta property=\"og:image:type\" content=\"image\/jpeg\" \/>\n<meta name=\"author\" content=\"Alain Dieul\" \/>\n<meta name=\"twitter:card\" content=\"summary_large_image\" \/>\n<meta name=\"twitter:label1\" content=\"Written by\" \/>\n\t<meta name=\"twitter:data1\" content=\"Alain Dieul\" \/>\n\t<meta name=\"twitter:label2\" content=\"Est. reading time\" \/>\n\t<meta name=\"twitter:data2\" content=\"2 minutes\" \/>\n<script type=\"application\/ld+json\" class=\"yoast-schema-graph\">{\"@context\":\"https:\/\/schema.org\",\"@graph\":[{\"@type\":\"Article\",\"@id\":\"https:\/\/cdn.eenewseurope.com\/fr\/ip-phy-de-connectivite-puce-a-puce\/#article\",\"isPartOf\":{\"@id\":\"https:\/\/cdn.eenewseurope.com\/fr\/ip-phy-de-connectivite-puce-a-puce\/\"},\"author\":{\"name\":\"Alain Dieul\",\"@id\":\"https:\/\/www.eenewseurope.com\/en\/#\/schema\/person\/568c789a4794bd460460501ba91f5daf\"},\"headline\":\"IP PHY de connectivit\u00e9 puce \u00e0 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