{"id":65198,"date":"2020-01-29T11:01:28","date_gmt":"2020-01-29T11:01:28","guid":{"rendered":"https:\/\/\/intel-rejoint-lalliance-open-source-chips\/"},"modified":"2020-01-29T11:01:28","modified_gmt":"2020-01-29T11:01:28","slug":"intel-rejoint-lalliance-open-source-chips","status":"publish","type":"post","link":"https:\/\/www.ecinews.fr\/fr\/intel-rejoint-lalliance-open-source-chips\/","title":{"rendered":"Intel rejoint l&rsquo;Alliance open source CHIPS"},"content":{"rendered":"<p><span class=\"tlid-translation translation\" lang=\"fr\">Intel a utilis\u00e9 le bus AIB dans ses propres composants multi-puces.<\/p>\n<p>La CHIPS Alliance a \u00e9t\u00e9 fond\u00e9e en 2019 par la Linux Foundation avec une charte pour h\u00e9berger et organiser du code open source de haute qualit\u00e9 pertinent pour la conception de dispositifs en silicium (voir <\/span> <a href=\"https:\/\/www.eenewsanalog.com\/news\/linux-meet-risc-v-open-source-groups-team\">Linux meet RISC-V: open source groups team up<\/a><span class=\"tlid-translation translation\" lang=\"fr\"> les groupes open source s&rsquo;associent). Les premiers membres incluent Esperanto Technologies, Google, SiFive et Western Digital qui ont \u00e9t\u00e9 rejoints par Alibaba, Samsung, Futurewei (la branche de recherche am\u00e9ricaine de Hauwei) et Imperas, entre autres.<\/span><\/p>\n<p><span class=\"tlid-translation translation\" lang=\"fr\">Le projet CHIPS Alliance d\u00e9veloppe et h\u00e9berge du code de niveau RTL (transfert de registre) et des outils de d\u00e9veloppement logiciel pour la conception de CPU open source, de SoCs, d&rsquo;IP d&rsquo;interconnexion et de p\u00e9riph\u00e9riques pour FPGA et silicium personnalis\u00e9. Ces c\u0153urs IP open source sont destin\u00e9s \u00e0 \u00eatre utilis\u00e9s dans l&rsquo;\u00e9lectronique grand public et mobile, l&rsquo;informatique et les applications Internet des objets (IoT).<\/span><\/p>\n<p><span class=\"tlid-translation translation\" lang=\"fr\">Intel partagera son bus d&rsquo;interface avanc\u00e9e (AIB : <\/span>Advanced Interface Bus <span class=\"tlid-translation translation\" lang=\"fr\">) en tant que composant open source comme norme de niveau PHY libre de droits pour connecter plusieurs puces dans le m\u00eame bo\u00eetier.<\/span><\/p>\n<p><span class=\"tlid-translation translation\" lang=\"fr\">Cet effort vise \u00e0 encourager un environnement industriel dans lequel les IP silicium peuvent \u00eatre d\u00e9velopp\u00e9s comme \u00ab\u00a0chiplets\u00a0\u00bb en utilisant n&rsquo;importe quel processus semiconducteur et int\u00e9gr\u00e9 avec d&rsquo;autres puces dans un seul composant. Une adoption et une prise en charge plus larges de \u00ab\u00a0chiplets\u00a0\u00bb compatibles AIB aideront les d\u00e9veloppeurs de composants \u00e0 aller au-del\u00e0 des limites de la fabrication de semiconducteurs monolithiques traditionnels et \u00e0 r\u00e9duire les co\u00fbts de d\u00e9veloppement. La CHIPS Alliance a d\u00e9clar\u00e9 que la donation du bus AIB d&rsquo;Intel aiderait \u00e0 d\u00e9velopper un \u00e9cosyst\u00e8me de \u00ab\u00a0chiplets\u00a0\u00bb et \u00e0 soutenir plus d&rsquo;innovation dans les composants via une int\u00e9gration h\u00e9t\u00e9rog\u00e8ne.<\/span><\/p>\n<p><span class=\"tlid-translation translation\" lang=\"fr\">Les sp\u00e9cifications AIB et d&rsquo;autres \u00e9l\u00e9ments seront d\u00e9velopp\u00e9s plus avant dans le groupe de travail Interconnexions de l&rsquo;Alliance CHIPS et plac\u00e9s dans le github de l&rsquo;Alliance CHIPS (<\/span><a href=\"http:\/\/github.com\/chipsalliance\/aib-phy-hardware\">CHIPS Alliance github)<\/a><span class=\"tlid-translation translation\" lang=\"fr\">.<\/span><\/p>\n<p><span class=\"tlid-translation translation\" lang=\"fr\">Intel rejoint l&rsquo;organisation CHIPS Alliance \u00e0 son plus haut niveau \u00ab\u00a0platinum\u00a0\u00bb, aux c\u00f4t\u00e9s d&rsquo;Alibaba, Google, SiFive et Western Digital. Cela donne \u00e0 l&rsquo;entreprise un si\u00e8ge au conseil d&rsquo;administration. Zvonimir Bandi\u0107, est pr\u00e9sident de CHIPS Alliance et directeur principal de l&rsquo;architecture des plates-formes de nouvelle g\u00e9n\u00e9ration chez Western Digital.<\/span><\/p>\n<p>lire aussi:<\/p>\n<p><a href=\"https:\/\/www.electronique-eci.com\/news\/un-processeur-risc-v-made-china-pour-contourner-trump\">Un processeur RISC-V made in China pour contourner Trump ?<\/a><\/p>\n<p><a href=\"https:\/\/www.electronique-eci.com\/news\/x-fab-silicon-fabrique-les-premiers-mcu-risc-v-open-source\">X-FAB Silicon fabrique les premiers MCU RISC-V open source <\/a><\/p>\n<p><a href=\"https:\/\/www.electronique-eci.com\/news\/kalray-partenaire-et-fournisseur-dune-technologie-cle-du-processeur-europeen-epi\">Kalray partenaire et fournisseur d\u2019une technologie cl\u00e9 du processeur europ\u00e9en EPI <\/a><\/p>\n<p><a href=\"https:\/\/Avec EPI, l'Europe cherche l'ind\u00e9pendance pour ses syst\u00e8mes exascale\">Avec EPI, l&rsquo;Europe cherche l&rsquo;ind\u00e9pendance pour ses syst\u00e8mes exascale <\/a><\/p>\n<p><a href=\"https:\/\/www.electronique-eci.com\/news\/nvidia-rachete-mellanox-pour-69-milliards\">Nvidia rach\u00e8te Mellanox pour $6.9 milliards <\/a><\/p>\n<p><strong>Related links and articles: <\/strong><\/p>\n<p><a href=\"http:\/\/www.intel.com\/\">www.intel.com<\/a><\/p>\n<p><a href=\"http:\/\/www.chipsalliance.org\/\">www.chipsalliance.org<\/a><\/p>\n<p><a href=\"http:\/\/www.linuxfoundation.org\/\">www.linuxfoundation.org<\/a><\/p>\n<p><strong>News articles:<\/strong><\/p>\n<p><a href=\"https:\/\/www.eenewsanalog.com\/news\/linux-meet-risc-v-open-source-groups-team\">Linux meet RISC-V: open source groups team up<\/a><\/p>\n<p>&nbsp;<\/p>\n<hr \/>\n<p>&nbsp;<\/p>\n","protected":false},"excerpt":{"rendered":"<p>Intel a rejoint la CHIPS Alliance, un consortium form\u00e9 pour promouvoir le hardware ouvert, et contribue son architecture de bus \u00ab\u00a0Advanced Interface Bus\u00a0\u00bb (AIB) pour encourager la fabrication de style \u00ab\u00a0chiplet\u00a0\u00bb.<\/p>\n","protected":false},"author":22,"featured_media":65199,"comment_status":"closed","ping_status":"closed","sticky":false,"template":"","format":"standard","meta":{"_acf_changed":false,"footnotes":""},"categories":[],"tags":[889,920,894,895,897,899,902,903,919,913,905,906,908,916,910,914,915],"domains":[47],"ppma_author":[1149],"class_list":["post-65198","post","type-post","status-publish","format-standard","has-post-thumbnail","hentry","tag-analog-fr","tag-artificialintelligence-fr","tag-boards-embedded-cards-fr","tag-developmentkits-fr","tag-displays-interfaces-fr","tag-eda-cad-tools-fr","tag-flexibleelectronics-fr","tag-interconnect-cables-fr","tag-iot-fr","tag-materials-processes-fr","tag-memory-data-storage-fr","tag-mpus-mcus-fr","tag-plds-fpgas-asics-fr","tag-rf-transmission-fr","tag-sensing-conditioning-fr","tag-wearables-fr","tag-wireless-communications-fr","domains-electronique-eci"],"acf":[],"yoast_head":"<title>Intel rejoint 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