{"id":61159,"date":"2020-03-18T08:31:44","date_gmt":"2020-03-18T08:31:44","guid":{"rendered":"https:\/\/\/cadence-collabore-avec-stmicroelectronics\/"},"modified":"2020-03-18T08:31:44","modified_gmt":"2020-03-18T08:31:44","slug":"cadence-collabore-avec-stmicroelectronics","status":"publish","type":"post","link":"https:\/\/www.ecinews.fr\/fr\/cadence-collabore-avec-stmicroelectronics\/","title":{"rendered":"Cadence collabore avec STMicroelectronics"},"content":{"rendered":"

Cadence a fourni \u00e0 ST l\u2019architecture IP critique, certains sous-blocs de propri\u00e9t\u00e9 intellectuelle et le support de conception correspondant, en s\u2019appuyant sur ses investissements consacr\u00e9s \u00e0 la technologie de s\u00e9rialiseur-d\u00e9s\u00e9rialiseur PAM4 56G et 112G. Pour sa part, ST a d\u00e9velopp\u00e9 l\u2019int\u00e9gralit\u00e9 du c\u0153ur du SerDes en mettant \u00e0 profit son vaste savoir-faire dans ce domaine.<\/p>\n

Le vaste portefeuille de propri\u00e9t\u00e9 intellectuelle de Cadence, qui comprend notamment le s\u00e9rialiseur-d\u00e9s\u00e9rialiseur PAM4 multid\u00e9bits 112G, et la technologie de conception num\u00e9rique et de validation, avec le syst\u00e8me d\u2019impl\u00e9mentation physique Innovus, s\u2019inscrivent tous deux dans le cadre de la strat\u00e9gie Intelligent System Design\u2122 de Cadence, dont la vocation est d\u2019aider ses clients \u00e0 atteindre l\u2019excellence dans la conception de syst\u00e8mes sur puce (SoC).<\/p>\n

www.cadence.com\/go\/56gserdesip<\/a><\/p>\n

Cadence annonce la premi\u00e8re IP de v\u00e9rification multiprotocoles pour les interfaces PHY<\/a><\/h3>\n

Cadence annonce une nouvelle solution pour acc\u00e9l\u00e9rer la validation des contraintes<\/a><\/h3>\n

Le nouveau DSP de Cadence multiplie par deux les performances des applications de vision et d\u2019IA<\/a><\/h3>\n","protected":false},"excerpt":{"rendered":"

Cadence Design Systems, Inc. a travaill\u00e9 avec STMicroelectronics sur le tape-out d\u2019un s\u00e9rialiseur-d\u00e9s\u00e9rialiseur (SerDes) 56G \u00e0 tr\u00e8s courte port\u00e9e (VSR \u2014 Very Short Range) en technologie de 7 nm pour un syst\u00e8me sur puce (SoC) destin\u00e9 aux march\u00e9s des r\u00e9seaux, du cloud et des centres de donn\u00e9es. <\/p>\n","protected":false},"author":9,"featured_media":61160,"comment_status":"closed","ping_status":"closed","sticky":false,"template":"","format":"standard","meta":{"_acf_changed":false,"footnotes":""},"categories":[],"tags":[],"domains":[47],"ppma_author":[1141],"class_list":["post-61159","post","type-post","status-publish","format-standard","has-post-thumbnail","hentry","domains-electronique-eci"],"acf":[],"yoast_head":"Cadence collabore avec STMicroelectronics ...<\/title>\n<meta name=\"description\" content=\"Cadence Design Systems, Inc. a travaill\u00e9 avec STMicroelectronics sur le tape-out d\u2019un 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