\u00ab\u00a0Apr\u00e8s la publication cette ann\u00e9e de la sp\u00e9cification PCIe 7.0, la sp\u00e9cification PCIe 8.0 doublera le d\u00e9bit de donn\u00e9es \u00e0 256 GT\/s, maintenant notre tradition de doubler la bande passante tous les trois ans pour soutenir les applications de nouvelle g\u00e9n\u00e9ration\u00a0\u00bb, a d\u00e9clar\u00e9 Al Yanes, pr\u00e9sident du PCI-SIG et pr\u00e9sident du conseil d’administration. \u00ab\u00a0Avec l’augmentation du d\u00e9bit de donn\u00e9es requis dans l’IA et d’autres applications, il y a toujours une forte demande de haute performance. La technologie PCIe continuera \u00e0 fournir une interconnexion d’E\/S \u00e9conomique, \u00e0 large bande passante et \u00e0 faible latence pour r\u00e9pondre aux besoins de l’industrie.\u00a0\u00bb<\/p>\n
![\"\"](\"https:\/\/www.eenewseurope.com\/wp-content\/uploads\/2025\/08\/PCISIG_Speeds_Feeds_2025-1-1024x627.jpg\")
Vitesses PCIe Source : PCI-SIG<\/p><\/div>\n
\u00ab\u00a0Comme l’intelligence artificielle et d’autres applications \u00e0 forte intensit\u00e9 de donn\u00e9es continuent \u00e0 \u00e9voluer rapidement, la demande de technologie PCIe sera soutenue \u00e0 long terme en raison de sa bande passante \u00e9lev\u00e9e, de son \u00e9volutivit\u00e9 et de son efficacit\u00e9 \u00e9nerg\u00e9tique\u00a0\u00bb, a d\u00e9clar\u00e9 Reece Hayden, analyste principal chez ABI Research. \u00ab\u00a0Les r\u00e9seaux de centres de donn\u00e9es se pr\u00e9parent d\u00e9j\u00e0 \u00e0 mettre en \u0153uvre la technologie PCIe 6.0 et montrent un grand int\u00e9r\u00eat pour la sp\u00e9cification PCIe 7.0. L’introduction de la sp\u00e9cification PCIe 8.0 garantit que les exigences de l’industrie en mati\u00e8re de bande passante seront prises en charge \u00e0 l’avenir.<\/p>\n
La sp\u00e9cification PCIe 8.0 vise \u00e0 soutenir les applications \u00e9mergentes telles que l’intelligence artificielle\/l’apprentissage machine, les r\u00e9seaux \u00e0 haut d\u00e9bit, l’informatique de pointe et l’informatique quantique, ainsi que les march\u00e9s \u00e0 forte intensit\u00e9 de donn\u00e9es tels que l’automobile, les centres de donn\u00e9es \u00e0 grande \u00e9chelle, l’informatique \u00e0 haute performance (HPC) et le secteur militaire\/a\u00e9rospatial.<\/p>\n
PCI Express est un protocole cl\u00e9 pour le consortium Universal Chiplet Interconnect Express (UCIe) qui a \u00e9galement annonc\u00e9 UCIe 3.0.<\/p>\n
- \n
- L’IP UCIe 2nm prend en charge des donn\u00e9es de puce \u00e0 puce \u00e0 36 Gb\/s<\/a><\/li>\n
- La premi\u00e8re puce optique CMOS UCIe atteint 8Tbit\/s<\/a><\/li>\n<\/ul>\n
La version 3.0 de la norme ouverte pour les interconnexions entre les puces \u00e0 l’int\u00e9rieur d’un bo\u00eetier double le d\u00e9bit de donn\u00e9es avec la prise en charge des transferts \u00e0 48 GT\/s et 64 GT\/s, ainsi que des mises \u00e0 jour architecturales incr\u00e9mentielles pour r\u00e9pondre \u00e0 la demande croissante de l’industrie pour des solutions interop\u00e9rables \u00e0 grande vitesse pour les puces.<\/p>\n
La sp\u00e9cification UCIe 3.0 introduit \u00e9galement des am\u00e9liorations telles que le recalibrage en cours d’ex\u00e9cution pour une meilleure efficacit\u00e9 \u00e9nerg\u00e9tique gr\u00e2ce \u00e0 l’ajustement de la liaison pendant le fonctionnement en r\u00e9utilisant les \u00e9tats d’initialisation. Elle comprend \u00e9galement une bande lat\u00e9rale \u00e9tendue qui prend en charge des con\ufb01gurations multi-puces plus \ufb02exibles avec des liens d’une longueur maximale de 100 mm.<\/p>\n
La prise en charge des protocoles de transmission continue par le biais de mappages permet un flux de donn\u00e9es ininterrompu en mode brut pour de nouvelles applications telles que la connectivit\u00e9 entre les puces SoC et DSP.<\/p>\n
Le t\u00e9l\u00e9chargement pr\u00e9coce de logiciels avec un protocole de transport de gestion normalis\u00e9 (MTP) et les paquets \u00e0 bande lat\u00e9rale prioritaire augmentent la r\u00e9activit\u00e9 et la fiabilit\u00e9 du syst\u00e8me. Il s’agit de fonctions de g\u00e9rabilit\u00e9 optionnelles que les concepteurs peuvent mettre en \u0153uvre s’ils choisissent une signalisation d\u00e9terministe et \u00e0 faible latence pour les \u00e9v\u00e9nements syst\u00e8me sensibles au temps.<\/p>\n
\u00ab\u00a0L’UCIe 3.0 repr\u00e9sente une \u00e9tape cruciale pour l’industrie des puces, car elle offre la vitesse, l’efficacit\u00e9 et la facilit\u00e9 de gestion n\u00e9cessaires \u00e0 la mise \u00e0 l’\u00e9chelle des conceptions multi-puces\u00a0\u00bb, a d\u00e9clar\u00e9 Cheolmin Park, pr\u00e9sident du consortium UCIe et vice-pr\u00e9sident de Samsung Electro-Mechanics. \u00ab\u00a0Avec des d\u00e9bits de donn\u00e9es accrus et des capacit\u00e9s de gestion \u00e9tendues, la prochaine g\u00e9n\u00e9ration de technologie UCIe permettra aux d\u00e9veloppeurs de cr\u00e9er des solutions SiP plus flexibles, interop\u00e9rables et performantes, alors que nous travaillons tous ensemble \u00e0 la construction d’un \u00e9cosyst\u00e8me de chiplets v\u00e9ritablement ouvert et interop\u00e9rable.\u00a0\u00bb<\/p>\n
La sp\u00e9ci\ufb01cation UCIe 3.0 est disponible sur demande \u00e0 l’adresse www.uciexpress.org\/speci\ufb01cations<\/a>.<\/p>\n
www.pcisig.com<\/a> ;<\/a> www.synopsys.com ;<\/a> www.uciexpress.org\/specifications<\/a><\/p>\n
<\/p>\n
<\/p>\n
<\/p>\n
<\/p>\n","protected":false},"excerpt":{"rendered":"
Le groupe d’int\u00e9r\u00eat sp\u00e9cial (SIG) PCI vise des vitesses de 256GTransactions\/s avec PCI Express (PCIe) 8.0 afin de fournir des liens plus rapides entre les puces pour l’IA. Parall\u00e8lement, le consortium Universal Chiplet Interconnect Express (UCIe) a annonc\u00e9 UCIe 3.0. La sp\u00e9cification PCIe 8.0 doublera les donn\u00e9es de la sp\u00e9cification PCIe 7.0 et sera disponible […]<\/p>\n","protected":false},"author":34,"featured_media":484165,"comment_status":"closed","ping_status":"closed","sticky":false,"template":"","format":"standard","meta":{"_acf_changed":false,"footnotes":""},"categories":[883],"tags":[3684,10336,10335],"domains":[47],"ppma_author":[3640,1153],"class_list":["post-484175","post","type-post","status-publish","format-standard","has-post-thumbnail","hentry","category-technologies","tag-interconnexion","tag-pcie-7","tag-pcie-8","domains-electronique-eci"],"acf":[],"yoast_head":"
PCIe 8.0 vise les 256GT\/s pour l'IA ...<\/title>\n<meta name=\"description\" content=\"Le groupe d'int\u00e9r\u00eat sp\u00e9cial (SIG) PCI vise 256GTransactions\/s avec PCIe 8.0 afin de fournir des liens plus rapides entre les puces pour l'IA\" \/>\n<meta name=\"robots\" content=\"index, follow, max-snippet:-1, max-image-preview:large, max-video-preview:-1\" \/>\n<link rel=\"canonical\" href=\"https:\/\/www.ecinews.fr\/fr\/wp-json\/wp\/v2\/posts\/484175\/\" \/>\n<meta property=\"og:locale\" content=\"fr_FR\" \/>\n<meta property=\"og:type\" content=\"article\" \/>\n<meta property=\"og:title\" content=\"PCIe 8.0 vise les 256GT\/s pour l'IA\" \/>\n<meta property=\"og:description\" content=\"Le groupe d'int\u00e9r\u00eat sp\u00e9cial (SIG) PCI vise 256GTransactions\/s avec PCIe 8.0 afin de fournir des liens plus rapides entre les puces pour l'IA\" \/>\n<meta property=\"og:url\" content=\"https:\/\/www.ecinews.fr\/fr\/wp-json\/wp\/v2\/posts\/484175\/\" \/>\n<meta property=\"og:site_name\" content=\"EENewsEurope\" \/>\n<meta property=\"article:published_time\" content=\"2025-08-06T14:07:33+00:00\" \/>\n<meta property=\"og:image\" content=\"https:\/\/www.ecinews.fr\/wp-content\/uploads\/2025\/08\/PCI-SIG_Law_Graphic-8.0-scaled.jpg\" \/>\n\t<meta property=\"og:image:width\" content=\"1080\" \/>\n\t<meta property=\"og:image:height\" content=\"1080\" \/>\n\t<meta property=\"og:image:type\" content=\"image\/jpeg\" \/>\n<meta name=\"author\" content=\"Nick Flaherty, A Delapalisse\" \/>\n<meta name=\"twitter:card\" content=\"summary_large_image\" \/>\n<meta name=\"twitter:label1\" content=\"Written by\" \/>\n\t<meta name=\"twitter:data1\" content=\"A Delapalisse\" \/>\n\t<meta name=\"twitter:label2\" content=\"Est. reading time\" \/>\n\t<meta name=\"twitter:data2\" content=\"4 minutes\" \/>\n<script type=\"application\/ld+json\" class=\"yoast-schema-graph\">{\"@context\":\"https:\/\/schema.org\",\"@graph\":[{\"@type\":\"Article\",\"@id\":\"https:\/\/www.ecinews.fr\/fr\/pcie-8-0-vise-les-256gt-s-pour-lia\/#article\",\"isPartOf\":{\"@id\":\"https:\/\/www.ecinews.fr\/fr\/pcie-8-0-vise-les-256gt-s-pour-lia\/\"},\"author\":{\"name\":\"A Delapalisse\",\"@id\":\"https:\/\/www.eenewseurope.com\/fr\/#\/schema\/person\/0aa2cfb0bd8949724a68cbac8d8321b4\"},\"headline\":\"PCIe 8.0 vise les 256GT\/s pour l’IA\",\"datePublished\":\"2025-08-06T14:07:33+00:00\",\"dateModified\":\"2025-08-06T14:07:33+00:00\",\"mainEntityOfPage\":{\"@id\":\"https:\/\/www.ecinews.fr\/fr\/pcie-8-0-vise-les-256gt-s-pour-lia\/\"},\"wordCount\":871,\"publisher\":{\"@id\":\"https:\/\/www.eenewseurope.com\/fr\/#organization\"},\"keywords\":[\"interconnexion\",\"PCIe 7\",\"PCIe 8\"],\"articleSection\":[\"Technologies\"],\"inLanguage\":\"fr-FR\"},{\"@type\":\"WebPage\",\"@id\":\"https:\/\/www.ecinews.fr\/fr\/pcie-8-0-vise-les-256gt-s-pour-lia\/\",\"url\":\"https:\/\/www.ecinews.fr\/fr\/pcie-8-0-vise-les-256gt-s-pour-lia\/\",\"name\":\"PCIe 8.0 vise les 256GT\/s pour l'IA -\",\"isPartOf\":{\"@id\":\"https:\/\/www.eenewseurope.com\/fr\/#website\"},\"datePublished\":\"2025-08-06T14:07:33+00:00\",\"dateModified\":\"2025-08-06T14:07:33+00:00\",\"description\":\"Le groupe d'int\u00e9r\u00eat sp\u00e9cial (SIG) PCI vise 256GTransactions\/s avec PCIe 8.0 afin de fournir des liens plus rapides entre les puces pour l'IA\",\"breadcrumb\":{\"@id\":\"https:\/\/www.ecinews.fr\/fr\/pcie-8-0-vise-les-256gt-s-pour-lia\/#breadcrumb\"},\"inLanguage\":\"fr-FR\",\"potentialAction\":[{\"@type\":\"ReadAction\",\"target\":[\"https:\/\/www.ecinews.fr\/fr\/pcie-8-0-vise-les-256gt-s-pour-lia\/\"]}]},{\"@type\":\"BreadcrumbList\",\"@id\":\"https:\/\/www.ecinews.fr\/fr\/pcie-8-0-vise-les-256gt-s-pour-lia\/#breadcrumb\",\"itemListElement\":[{\"@type\":\"ListItem\",\"position\":1,\"name\":\"Home\",\"item\":\"https:\/\/test.eenewseurope.com\/fr\/\"},{\"@type\":\"ListItem\",\"position\":2,\"name\":\"PCIe 8.0 vise les 256GT\/s pour l’IA\"}]},{\"@type\":\"WebSite\",\"@id\":\"https:\/\/www.eenewseurope.com\/fr\/#website\",\"url\":\"https:\/\/www.eenewseurope.com\/fr\/\",\"name\":\"EENewsEurope\",\"description\":\"Just another WordPress site\",\"publisher\":{\"@id\":\"https:\/\/www.eenewseurope.com\/fr\/#organization\"},\"potentialAction\":[{\"@type\":\"SearchAction\",\"target\":{\"@type\":\"EntryPoint\",\"urlTemplate\":\"https:\/\/www.eenewseurope.com\/fr\/?s={search_term_string}\"},\"query-input\":\"required name=search_term_string\"}],\"inLanguage\":\"fr-FR\"},{\"@type\":\"Organization\",\"@id\":\"https:\/\/www.eenewseurope.com\/fr\/#organization\",\"name\":\"EENewsEurope\",\"url\":\"https:\/\/www.eenewseurope.com\/fr\/\",\"logo\":{\"@type\":\"ImageObject\",\"inLanguage\":\"fr-FR\",\"@id\":\"https:\/\/www.eenewseurope.com\/fr\/#\/schema\/logo\/image\/\",\"url\":\"https:\/\/www.ecinews.fr\/wp-content\/uploads\/2022\/02\/logo-1.jpg\",\"contentUrl\":\"https:\/\/www.ecinews.fr\/wp-content\/uploads\/2022\/02\/logo-1.jpg\",\"width\":283,\"height\":113,\"caption\":\"EENewsEurope\"},\"image\":{\"@id\":\"https:\/\/www.eenewseurope.com\/fr\/#\/schema\/logo\/image\/\"}},{\"@type\":\"Person\",\"@id\":\"https:\/\/www.eenewseurope.com\/fr\/#\/schema\/person\/0aa2cfb0bd8949724a68cbac8d8321b4\",\"name\":\"A Delapalisse\",\"image\":{\"@type\":\"ImageObject\",\"inLanguage\":\"fr-FR\",\"@id\":\"https:\/\/www.eenewseurope.com\/fr\/#\/schema\/person\/image\/211ac42237c2e9683c0964086c393cb4\",\"url\":\"https:\/\/secure.gravatar.com\/avatar\/ad45a8c5da24bc9c7c4940dd1c48a695?s=96&d=mm&r=g\",\"contentUrl\":\"https:\/\/secure.gravatar.com\/avatar\/ad45a8c5da24bc9c7c4940dd1c48a695?s=96&d=mm&r=g\",\"caption\":\"A Delapalisse\"},\"sameAs\":[\"http:\/\/ECI\"]}]}<\/script>","yoast_head_json":{"title":"PCIe 8.0 vise les 256GT\/s pour l'IA ...","description":"Le groupe d'int\u00e9r\u00eat sp\u00e9cial (SIG) PCI vise 256GTransactions\/s avec PCIe 8.0 afin de fournir des liens plus rapides entre les puces pour l'IA","robots":{"index":"index","follow":"follow","max-snippet":"max-snippet:-1","max-image-preview":"max-image-preview:large","max-video-preview":"max-video-preview:-1"},"canonical":"https:\/\/www.ecinews.fr\/fr\/wp-json\/wp\/v2\/posts\/484175\/","og_locale":"fr_FR","og_type":"article","og_title":"PCIe 8.0 vise les 256GT\/s pour l'IA","og_description":"Le groupe d'int\u00e9r\u00eat sp\u00e9cial (SIG) PCI vise 256GTransactions\/s avec PCIe 8.0 afin de fournir des liens plus rapides entre les puces pour l'IA","og_url":"https:\/\/www.ecinews.fr\/fr\/wp-json\/wp\/v2\/posts\/484175\/","og_site_name":"EENewsEurope","article_published_time":"2025-08-06T14:07:33+00:00","og_image":[{"width":1080,"height":1080,"url":"https:\/\/www.ecinews.fr\/wp-content\/uploads\/2025\/08\/PCI-SIG_Law_Graphic-8.0-scaled.jpg","type":"image\/jpeg"}],"author":"Nick Flaherty, A Delapalisse","twitter_card":"summary_large_image","twitter_misc":{"Written by":"A Delapalisse","Est. reading time":"4 minutes"},"schema":{"@context":"https:\/\/schema.org","@graph":[{"@type":"Article","@id":"https:\/\/www.ecinews.fr\/fr\/pcie-8-0-vise-les-256gt-s-pour-lia\/#article","isPartOf":{"@id":"https:\/\/www.ecinews.fr\/fr\/pcie-8-0-vise-les-256gt-s-pour-lia\/"},"author":{"name":"A Delapalisse","@id":"https:\/\/www.eenewseurope.com\/fr\/#\/schema\/person\/0aa2cfb0bd8949724a68cbac8d8321b4"},"headline":"PCIe 8.0 vise les 256GT\/s pour l’IA","datePublished":"2025-08-06T14:07:33+00:00","dateModified":"2025-08-06T14:07:33+00:00","mainEntityOfPage":{"@id":"https:\/\/www.ecinews.fr\/fr\/pcie-8-0-vise-les-256gt-s-pour-lia\/"},"wordCount":871,"publisher":{"@id":"https:\/\/www.eenewseurope.com\/fr\/#organization"},"keywords":["interconnexion","PCIe 7","PCIe 8"],"articleSection":["Technologies"],"inLanguage":"fr-FR"},{"@type":"WebPage","@id":"https:\/\/www.ecinews.fr\/fr\/pcie-8-0-vise-les-256gt-s-pour-lia\/","url":"https:\/\/www.ecinews.fr\/fr\/pcie-8-0-vise-les-256gt-s-pour-lia\/","name":"PCIe 8.0 vise les 256GT\/s pour l'IA -","isPartOf":{"@id":"https:\/\/www.eenewseurope.com\/fr\/#website"},"datePublished":"2025-08-06T14:07:33+00:00","dateModified":"2025-08-06T14:07:33+00:00","description":"Le groupe d'int\u00e9r\u00eat sp\u00e9cial (SIG) PCI vise 256GTransactions\/s avec PCIe 8.0 afin de fournir des liens plus rapides entre les puces pour l'IA","breadcrumb":{"@id":"https:\/\/www.ecinews.fr\/fr\/pcie-8-0-vise-les-256gt-s-pour-lia\/#breadcrumb"},"inLanguage":"fr-FR","potentialAction":[{"@type":"ReadAction","target":["https:\/\/www.ecinews.fr\/fr\/pcie-8-0-vise-les-256gt-s-pour-lia\/"]}]},{"@type":"BreadcrumbList","@id":"https:\/\/www.ecinews.fr\/fr\/pcie-8-0-vise-les-256gt-s-pour-lia\/#breadcrumb","itemListElement":[{"@type":"ListItem","position":1,"name":"Home","item":"https:\/\/test.eenewseurope.com\/fr\/"},{"@type":"ListItem","position":2,"name":"PCIe 8.0 vise les 256GT\/s pour l’IA"}]},{"@type":"WebSite","@id":"https:\/\/www.eenewseurope.com\/fr\/#website","url":"https:\/\/www.eenewseurope.com\/fr\/","name":"EENewsEurope","description":"Just another WordPress site","publisher":{"@id":"https:\/\/www.eenewseurope.com\/fr\/#organization"},"potentialAction":[{"@type":"SearchAction","target":{"@type":"EntryPoint","urlTemplate":"https:\/\/www.eenewseurope.com\/fr\/?s={search_term_string}"},"query-input":"required name=search_term_string"}],"inLanguage":"fr-FR"},{"@type":"Organization","@id":"https:\/\/www.eenewseurope.com\/fr\/#organization","name":"EENewsEurope","url":"https:\/\/www.eenewseurope.com\/fr\/","logo":{"@type":"ImageObject","inLanguage":"fr-FR","@id":"https:\/\/www.eenewseurope.com\/fr\/#\/schema\/logo\/image\/","url":"https:\/\/www.ecinews.fr\/wp-content\/uploads\/2022\/02\/logo-1.jpg","contentUrl":"https:\/\/www.ecinews.fr\/wp-content\/uploads\/2022\/02\/logo-1.jpg","width":283,"height":113,"caption":"EENewsEurope"},"image":{"@id":"https:\/\/www.eenewseurope.com\/fr\/#\/schema\/logo\/image\/"}},{"@type":"Person","@id":"https:\/\/www.eenewseurope.com\/fr\/#\/schema\/person\/0aa2cfb0bd8949724a68cbac8d8321b4","name":"A Delapalisse","image":{"@type":"ImageObject","inLanguage":"fr-FR","@id":"https:\/\/www.eenewseurope.com\/fr\/#\/schema\/person\/image\/211ac42237c2e9683c0964086c393cb4","url":"https:\/\/secure.gravatar.com\/avatar\/ad45a8c5da24bc9c7c4940dd1c48a695?s=96&d=mm&r=g","contentUrl":"https:\/\/secure.gravatar.com\/avatar\/ad45a8c5da24bc9c7c4940dd1c48a695?s=96&d=mm&r=g","caption":"A Delapalisse"},"sameAs":["http:\/\/ECI"]}]}},"authors":[{"term_id":3640,"user_id":0,"is_guest":1,"slug":"nick-flaherty","display_name":"Nick Flaherty","avatar_url":"https:\/\/secure.gravatar.com\/avatar\/?s=96&d=mm&r=g","0":null,"1":"","2":"","3":"","4":"","5":"","6":"","7":"","8":""},{"term_id":1153,"user_id":34,"is_guest":0,"slug":"adelapalisse","display_name":"A Delapalisse","avatar_url":"https:\/\/secure.gravatar.com\/avatar\/ad45a8c5da24bc9c7c4940dd1c48a695?s=96&d=mm&r=g","0":null,"1":"","2":"","3":"","4":"","5":"","6":"","7":"","8":""}],"_links":{"self":[{"href":"https:\/\/www.ecinews.fr\/fr\/wp-json\/wp\/v2\/posts\/484175"}],"collection":[{"href":"https:\/\/www.ecinews.fr\/fr\/wp-json\/wp\/v2\/posts"}],"about":[{"href":"https:\/\/www.ecinews.fr\/fr\/wp-json\/wp\/v2\/types\/post"}],"author":[{"embeddable":true,"href":"https:\/\/www.ecinews.fr\/fr\/wp-json\/wp\/v2\/users\/34"}],"replies":[{"embeddable":true,"href":"https:\/\/www.ecinews.fr\/fr\/wp-json\/wp\/v2\/comments?post=484175"}],"version-history":[{"count":0,"href":"https:\/\/www.ecinews.fr\/fr\/wp-json\/wp\/v2\/posts\/484175\/revisions"}],"wp:featuredmedia":[{"embeddable":true,"href":"https:\/\/www.ecinews.fr\/fr\/wp-json\/wp\/v2\/media\/484165"}],"wp:attachment":[{"href":"https:\/\/www.ecinews.fr\/fr\/wp-json\/wp\/v2\/media?parent=484175"}],"wp:term":[{"taxonomy":"category","embeddable":true,"href":"https:\/\/www.ecinews.fr\/fr\/wp-json\/wp\/v2\/categories?post=484175"},{"taxonomy":"post_tag","embeddable":true,"href":"https:\/\/www.ecinews.fr\/fr\/wp-json\/wp\/v2\/tags?post=484175"},{"taxonomy":"domains","embeddable":true,"href":"https:\/\/www.ecinews.fr\/fr\/wp-json\/wp\/v2\/domains?post=484175"},{"taxonomy":"author","embeddable":true,"href":"https:\/\/www.ecinews.fr\/fr\/wp-json\/wp\/v2\/ppma_author?post=484175"}],"curies":[{"name":"wp","href":"https:\/\/api.w.org\/{rel}","templated":true}]}} - La premi\u00e8re puce optique CMOS UCIe atteint 8Tbit\/s<\/a><\/li>\n<\/ul>\n