{"id":479218,"date":"2025-05-07T16:09:28","date_gmt":"2025-05-07T14:09:28","guid":{"rendered":"https:\/\/www.ecinews.fr\/?p=479218"},"modified":"2025-05-07T16:09:28","modified_gmt":"2025-05-07T14:09:28","slug":"semidynamics-presente-son-npu-risc-v-tout-en-un","status":"publish","type":"post","link":"https:\/\/www.ecinews.fr\/fr\/semidynamics-presente-son-npu-risc-v-tout-en-un\/","title":{"rendered":"SemiDynamics pr\u00e9sente son NPU RISC-V tout-en-un"},"content":{"rendered":"<p>La soci\u00e9t\u00e9 espagnole SemiDynamics a mis au point une unit\u00e9 de traitement neuronal (NPU) IP enti\u00e8rement programmable qui combine le traitement par CPU, vecteur et tenseur afin de fournir jusqu&rsquo;\u00e0 256 TOPS pour les mod\u00e8les de langage de grande taille et les syst\u00e8mes d&rsquo;IA.<\/p>\n<p>La NPU Cervell est bas\u00e9e sur l&rsquo;architecture RISC-V \u00e0 jeu d&rsquo;instructions ouvert qui s&rsquo;\u00e9tend de 8 \u00e0 64 c\u0153urs. Cela permet aux concepteurs d&rsquo;adapter les performances aux exigences des applications, de 8 TOPS INT8 \u00e0 1 GHz pour les d\u00e9ploiements compacts edge \u00e0 256 TOPS INT4 pour l&rsquo;inf\u00e9rence IA haut de gamme dans les puces de centres de donn\u00e9es.<\/p>\n<p>Elle fait suite au lancement de l&rsquo;architecture tout-en-un en d\u00e9cembre dernier, <a href=\"https:\/\/www.eenewseurope.com\/en\/white_papers\/semidynamics-details-all-in-one-ai-processor-technology\/\">d\u00e9taill\u00e9e dans ce livre blanc.<\/a><\/p>\n<p>\u00ab\u00a0Cervell est con\u00e7u pour une nouvelle \u00e8re de calcul de l&rsquo;IA, o\u00f9 les solutions standard ne suffisent pas. En tant que NPU, il offre les performances \u00e9volutives n\u00e9cessaires pour tout ce qui concerne l&rsquo;inf\u00e9rence edge et les grands mod\u00e8les de langage. Mais ce qui le distingue vraiment, c&rsquo;est la fa\u00e7on dont il est construit : enti\u00e8rement programmable, sans verrouillage gr\u00e2ce \u00e0 l&rsquo;ISA RISC-V ouverte, et profond\u00e9ment personnalisable jusqu&rsquo;au niveau de l&rsquo;instruction. Associ\u00e9 \u00e0 notre sous-syst\u00e8me de m\u00e9moire Gazillion Misses, Cervell \u00e9limine les goulets d&rsquo;\u00e9tranglement traditionnels des donn\u00e9es et offre aux concepteurs de puces une base puissante pour construire des solutions d&rsquo;IA diff\u00e9renci\u00e9es et performantes\u00a0\u00bb, d\u00e9clare Roger Espasa, PDG de Semidynamics.<\/p>\n<ul>\n<li><a href=\"https:\/\/www.eenewseurope.com\/en\/semidynamics-risc-v-ai-ip-selected-for-llm-applications\/\">RISC-V AI IP s\u00e9lectionn\u00e9 pour l&rsquo;application LLM<\/a><\/li>\n<li><a href=\"https:\/\/www.eenewseurope.com\/en\/semidynamics-launches-risc-v-sdk-adds-onnx-runtime-support\/\">Le SDK RISC-V ajoute la prise en charge de l&rsquo;ex\u00e9cution ONNX<\/a><\/li>\n<li><a href=\"https:\/\/www.eenewseurope.com\/en\/spanish-startup-performs-risc-v-open-core-surgery\/\">Une start-up espagnole pratique la chirurgie \u00e0 c\u0153ur ouvert<\/a><\/li>\n<\/ul>\n<p>Les NPU de Cervell sont sp\u00e9cialement con\u00e7ues pour acc\u00e9l\u00e9rer les op\u00e9rations \u00e0 forte intensit\u00e9 matricielle, ce qui permet d&rsquo;augmenter le d\u00e9bit, de r\u00e9duire la consommation d&rsquo;\u00e9nergie et d&rsquo;obtenir une r\u00e9ponse en temps r\u00e9el. En int\u00e9grant les capacit\u00e9s des NPU aux processeurs standard et au traitement vectoriel dans une architecture unifi\u00e9e, les concepteurs peuvent \u00e9liminer la latence et maximiser les performances de diverses t\u00e2ches d&rsquo;IA, des syst\u00e8mes de recommandation aux pipelines d&rsquo;apprentissage en profondeur.<\/p>\n<p>Les c\u0153urs Cervell sont \u00e9troitement int\u00e9gr\u00e9s au sous-syst\u00e8me de gestion de la m\u00e9moire Gazillion Misses. Cela permet d&rsquo;effectuer jusqu&rsquo;\u00e0 128 requ\u00eates simultan\u00e9es en m\u00e9moire, en \u00e9liminant les blocages de latence avec plus de 60 octets\/cycle de flux de donn\u00e9es continu. Il existe \u00e9galement un acc\u00e8s massivement parall\u00e8le \u00e0 la m\u00e9moire hors puce, essentiel pour l&rsquo;inf\u00e9rence de grands mod\u00e8les et le traitement de donn\u00e9es \u00e9parses.<\/p>\n<p>Cela permet de maintenir une saturation totale du pipeline, m\u00eame dans les applications gourmandes en bande passante telles que les syst\u00e8mes de recommandation et l&rsquo;apprentissage profond.<\/p>\n<p>Le noyau est <a href=\"https:\/\/www.eenewseurope.com\/en\/full-customisation-tool-for-semidynamics-risc-v-cores\/\">enti\u00e8rement personnalisable avec la possibilit\u00e9 d&rsquo;ajouter des instructions scalaires ou vectorielles<\/a>, de configurer des m\u00e9moires scratchpad et des FIFO E\/S personnalis\u00e9es et de d\u00e9finir des interfaces m\u00e9moire et des sch\u00e9mas de synchronisation pour fournir un <a href=\"https:\/\/www.eenewseurope.com\/en\/semidynamics-aims-to-future-proof-embedded-ai-chip-designs\/\">mat\u00e9riel d&rsquo;IA diff\u00e9renci\u00e9 \u00e0 l&rsquo;\u00e9preuve du temps.<\/a><\/p>\n<p>Cette personnalisation approfondie au niveau RTL, y compris l&rsquo;insertion d&rsquo;instructions d\u00e9finies par le client, permet aux entreprises d&rsquo;int\u00e9grer la propri\u00e9t\u00e9 intellectuelle unique directement dans la solution, prot\u00e9geant ainsi leur investissement ASIC contre l&rsquo;imitation et garantissant que la conception est enti\u00e8rement optimis\u00e9e en termes de puissance, de performance et de surface. Le mod\u00e8le de d\u00e9veloppement comprend des chutes de FPGA pr\u00e9coces et une v\u00e9rification parall\u00e8le afin de r\u00e9duire le temps de d\u00e9veloppement et les risques.<\/p>\n<table>\n<tbody>\n<tr>\n<td width=\"94\">\n<p>Configuration<\/p>\n<\/td>\n<td width=\"88\">\n<p>INT8 @ 1GHz<\/p>\n<\/td>\n<td width=\"88\">\n<p>INT4 \u00e0 1 GHz<\/p>\n<\/td>\n<td width=\"88\">\n<p>INT8 \u00e0 2 GHz<\/p>\n<\/td>\n<td width=\"88\">\n<p>INT4 \u00e0 2 GHz<\/p>\n<\/td>\n<\/tr>\n<tr>\n<td width=\"94\">\n<p>C8<\/p>\n<\/td>\n<td width=\"88\">\n<p>8 TOPS<\/p>\n<\/td>\n<td width=\"88\">\n<p>16 TOPS<\/p>\n<\/td>\n<td width=\"88\">\n<p>16 TOPS<\/p>\n<\/td>\n<td width=\"88\">\n<p>32 TOPS<\/p>\n<\/td>\n<\/tr>\n<tr>\n<td width=\"94\">\n<p>C16<\/p>\n<\/td>\n<td width=\"88\">\n<p>16 TOPS<\/p>\n<\/td>\n<td width=\"88\">\n<p>32 TOPS<\/p>\n<\/td>\n<td width=\"88\">\n<p>32 TOPS<\/p>\n<\/td>\n<td width=\"88\">\n<p>64 TOPS<\/p>\n<\/td>\n<\/tr>\n<tr>\n<td width=\"94\">\n<p>C32<\/p>\n<\/td>\n<td width=\"88\">\n<p>32 TOPS<\/p>\n<\/td>\n<td width=\"88\">\n<p>64 TOPS<\/p>\n<\/td>\n<td width=\"88\">\n<p>64 TOPS<\/p>\n<\/td>\n<td width=\"88\">\n<p>128 TOPS<\/p>\n<\/td>\n<\/tr>\n<tr>\n<td width=\"94\">\n<p>C64<\/p>\n<\/td>\n<td width=\"88\">\n<p>64 TOPS<\/p>\n<\/td>\n<td width=\"88\">\n<p>128 TOPS<\/p>\n<\/td>\n<td width=\"88\">\n<p>128 TOPS<\/p>\n<\/td>\n<td width=\"88\">\n<p>256 TOPS<\/p>\n<\/td>\n<\/tr>\n<\/tbody>\n<\/table>\n<p><a href=\"http:\/\/www.semidynamics.com\">www.semidynamics.com<\/a><\/p>\n<p>&nbsp;<\/p>\n","protected":false},"excerpt":{"rendered":"<p>La soci\u00e9t\u00e9 espagnole SemiDynamics a mis au point une unit\u00e9 de traitement neuronal (NPU) IP enti\u00e8rement programmable qui combine le traitement par CPU, vecteur et tenseur afin de fournir jusqu&rsquo;\u00e0 256 TOPS pour les mod\u00e8les de langage de grande taille et les syst\u00e8mes d&rsquo;IA. La NPU Cervell est bas\u00e9e sur l&rsquo;architecture RISC-V \u00e0 jeu d&rsquo;instructions [&hellip;]<\/p>\n","protected":false},"author":40,"featured_media":479094,"comment_status":"closed","ping_status":"closed","sticky":false,"template":"","format":"standard","meta":{"_acf_changed":false,"footnotes":""},"categories":[883],"tags":[2198,5151,1674,3641],"domains":[47],"ppma_author":[3640,6199],"class_list":["post-479218","post","type-post","status-publish","format-standard","has-post-thumbnail","hentry","category-technologies","tag-ia","tag-npu-fr","tag-risc-v-2","tag-risc-v-fr","domains-electronique-eci"],"acf":[],"yoast_head":"<title>SemiDynamics pr\u00e9sente son NPU RISC-V tout-en-un ...<\/title>\n<meta name=\"description\" content=\"SemiDynamics a d\u00e9velopp\u00e9 un NPU enti\u00e8rement programmable qui combine le traitement CPU, vectoriel et tensoriel\" \/>\n<meta name=\"robots\" content=\"index, follow, max-snippet:-1, max-image-preview:large, max-video-preview:-1\" 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