{"id":460919,"date":"2024-09-20T09:55:47","date_gmt":"2024-09-20T07:55:47","guid":{"rendered":"https:\/\/www.ecinews.fr\/?p=460919"},"modified":"2024-09-20T09:55:47","modified_gmt":"2024-09-20T07:55:47","slug":"sifive-ajoute-un-moteur-matriciel-au-processeur-risc-v-ai-ip","status":"publish","type":"post","link":"https:\/\/www.ecinews.fr\/fr\/sifive-ajoute-un-moteur-matriciel-au-processeur-risc-v-ai-ip\/","title":{"rendered":"SiFive ajoute un moteur matriciel au processeur RISC-V AI IP"},"content":{"rendered":"<h3>SiFive a lanc\u00e9 un processeur RISC-V IP avec un moteur matriciel et une extension personnalis\u00e9e pour la premi\u00e8re fois pour les applications d&rsquo;intelligence artificielle.<\/h3>\n<p>Les IP XM Series de <a href=\"https:\/\/www.eenewseurope.com\/en\/sifive-announces-4th-generation-of-risc-v-essential-ip-for-embedded-applications\/\">SiFive<\/a> comprennent un moteur matriciel d&rsquo;IA hautement \u00e9volutif pour les puces Edge AI et IoT ainsi que pour les appareils grand public, les v\u00e9hicules \u00e9lectriques et\/ou autonomes de nouvelle g\u00e9n\u00e9ration et les centres de donn\u00e9es.<\/p>\n<p>SiFive a \u00e9galement annonc\u00e9 son intention d&rsquo;ouvrir \u00e0 la source une impl\u00e9mentation de r\u00e9f\u00e9rence de sa SiFive Kernel Library (SKL).<\/p>\n<blockquote class=\"wp-embedded-content\" data-secret=\"cih7R6oWjE\"><p><a href=\"https:\/\/www.eenewseurope.com\/en\/sifive-moves-into-risc-v-datacentre-ai-processor-ip\/\">SiFive moves into RISC-V datacentre AI processor IP<\/a><\/p><\/blockquote>\n<p><iframe class=\"wp-embedded-content lazyload\" sandbox=\"allow-scripts\" security=\"restricted\" style=\"position: absolute; visibility: hidden;\" title=\"&#8220;SiFive moves into RISC-V datacentre AI processor IP&#8221; &#8212; eeNews Europe\" data-src=\"https:\/\/www.eenewseurope.com\/en\/sifive-moves-into-risc-v-datacentre-ai-processor-ip\/embed\/#?secret=OepjPQ8Ipj#?secret=cih7R6oWjE\" data-secret=\"cih7R6oWjE\" width=\"500\" height=\"282\" frameborder=\"0\" marginwidth=\"0\" marginheight=\"0\" scrolling=\"no\" src=\"data:image\/svg+xml;base64,PHN2ZyB3aWR0aD0iMSIgaGVpZ2h0PSIxIiB4bWxucz0iaHR0cDovL3d3dy53My5vcmcvMjAwMC9zdmciPjwvc3ZnPg==\" data-load-mode=\"1\"><\/iframe><\/p>\n<p>Le XM int\u00e8gre des moteurs scalaires, vectoriels et matriciels pour r\u00e9soudre les probl\u00e8mes de bande passante de la m\u00e9moire des conceptions d&rsquo;IA. Il y a quatre X-Cores par cluster, chacun avec deux unit\u00e9s vectorielles, et un cluster peut fournir 16 TOPS (INT8) ou 8 TFLOPS (BF16) par GHz. X-Cores par cluster. Il peut ex\u00e9cuter toutes les autres couches, par exemple les fonctions d&rsquo;activation, et ajoute de nouvelles instructions d&rsquo;acc\u00e9l\u00e9ration exponentielle personnalis\u00e9es.<\/p>\n<p>Les nouvelles instructions matricielles sont r\u00e9cup\u00e9r\u00e9es par l&rsquo;unit\u00e9 scalaire, les donn\u00e9es sources provenant des registres vectoriels, et les r\u00e9sultats sont envoy\u00e9s \u00e0 chaque accumulateur matriciel.<\/p>\n<p>Chaque grappe de la s\u00e9rie XM dispose d&rsquo;une bande passante m\u00e9moire soutenue de 1 To\/s. Les grappes peuvent acc\u00e9der \u00e0 la m\u00e9moire via un port \u00e0 large bande vers la SRAM pour les donn\u00e9es de mod\u00e8le ou via un port CHI pour l&rsquo;acc\u00e8s coh\u00e9rent \u00e0 la m\u00e9moire.<\/p>\n<blockquote class=\"wp-embedded-content\" data-secret=\"Ihs9LfjDGy\"><p><a href=\"https:\/\/www.eenewseurope.com\/en\/sifive-pqshield-encryption-deal-for-risc-v-designs\/\">SiFive, PQShield encryption deal for RISC-V designs<\/a><\/p><\/blockquote>\n<p><iframe class=\"wp-embedded-content lazyload\" sandbox=\"allow-scripts\" security=\"restricted\" style=\"position: absolute; visibility: hidden;\" title=\"&#8220;SiFive, PQShield encryption deal for RISC-V designs&#8221; &#8212; eeNews Europe\" data-src=\"https:\/\/www.eenewseurope.com\/en\/sifive-pqshield-encryption-deal-for-risc-v-designs\/embed\/#?secret=mZ27qplXBC#?secret=Ihs9LfjDGy\" data-secret=\"Ihs9LfjDGy\" width=\"500\" height=\"282\" frameborder=\"0\" marginwidth=\"0\" marginheight=\"0\" scrolling=\"no\" src=\"data:image\/svg+xml;base64,PHN2ZyB3aWR0aD0iMSIgaGVpZ2h0PSIxIiB4bWxucz0iaHR0cDovL3d3dy53My5vcmcvMjAwMC9zdmciPjwvc3ZnPg==\" data-load-mode=\"1\"><\/iframe><\/p>\n<p>\u00ab\u00a0De nombreuses entreprises constatent les avantages d&rsquo;un standard de processeur ouvert alors qu&rsquo;elles s&rsquo;efforcent de suivre le rythme rapide de l&rsquo;\u00e9volution de l&rsquo;IA. L&rsquo;IA joue sur les forces de SiFive avec la performance par watt et notre capacit\u00e9 unique \u00e0 aider les clients \u00e0 personnaliser leurs solutions \u00ab\u00a0, a d\u00e9clar\u00e9 Patrick Little, PDG de SiFive.<\/p>\n<p>\u00ab\u00a0RISC-V a \u00e9t\u00e9 d\u00e9velopp\u00e9 \u00e0 l&rsquo;origine pour prendre en charge efficacement les moteurs de calcul sp\u00e9cialis\u00e9s, y compris les op\u00e9rations en pr\u00e9cision mixte\u00a0\u00bb, a d\u00e9clar\u00e9 Krste Asanovic, fondateur et architecte en chef de SiFive. \u00ab\u00a0Cette caract\u00e9ristique, associ\u00e9e \u00e0 l&rsquo;inclusion d&rsquo;instructions vectorielles efficaces et \u00e0 la prise en charge d&rsquo;extensions sp\u00e9cialis\u00e9es dans l&rsquo;IA, est la raison pour laquelle bon nombre des plus grandes entreprises de centres de donn\u00e9es ont d\u00e9j\u00e0 adopt\u00e9 les acc\u00e9l\u00e9rateurs d&rsquo;IA RISC-V.\u00a0\u00bb<\/p>\n<p><a href=\"http:\/\/www.sifive.com\">www.sifive.com<\/a><\/p>\n<p>&nbsp;<\/p>\n","protected":false},"excerpt":{"rendered":"<p>SiFive a lanc\u00e9 un processeur RISC-V IP avec un moteur matriciel et une extension personnalis\u00e9e pour la premi\u00e8re fois pour les applications d&rsquo;intelligence artificielle. Les IP XM Series de SiFive comprennent un moteur matriciel d&rsquo;IA hautement \u00e9volutif pour les puces Edge AI et IoT ainsi que pour les appareils grand public, les v\u00e9hicules \u00e9lectriques et\/ou [&hellip;]<\/p>\n","protected":false},"author":34,"featured_media":460899,"comment_status":"closed","ping_status":"closed","sticky":false,"template":"","format":"standard","meta":{"_acf_changed":false,"footnotes":""},"categories":[883],"tags":[906,1674,3641],"domains":[47],"ppma_author":[3640,1153],"class_list":["post-460919","post","type-post","status-publish","format-standard","has-post-thumbnail","hentry","category-technologies","tag-mpus-mcus-fr","tag-risc-v-2","tag-risc-v-fr","domains-electronique-eci"],"acf":[],"yoast_head":"<title>SiFive ajoute un moteur matriciel au processeur RISC-V AI IP ...<\/title>\n<meta name=\"description\" content=\"SiFive a lanc\u00e9 un processeur RISC-V IP avec un moteur matriciel et une extension personnalis\u00e9e pour les applications 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