{"id":456728,"date":"2024-07-23T20:25:53","date_gmt":"2024-07-23T18:25:53","guid":{"rendered":"https:\/\/www.eenewseurope.com\/?p=456728"},"modified":"2024-07-23T20:25:53","modified_gmt":"2024-07-23T18:25:53","slug":"le-jedec-devoile-de-nouvelles-normes-de-memoire-pour-le-hpc-et-lia","status":"publish","type":"post","link":"https:\/\/www.ecinews.fr\/fr\/le-jedec-devoile-de-nouvelles-normes-de-memoire-pour-le-hpc-et-lia\/","title":{"rendered":"Le JEDEC d\u00e9voile de nouvelles normes de m\u00e9moire pour le HPC et l&rsquo;IA"},"content":{"rendered":"<h3><span style=\"font-size: 16px;\">La\u00a0\u00bb JEDEC Solid State Technology Association\u00a0\u00bb a annonc\u00e9 l&rsquo;arriv\u00e9e de nouvelles normes pour les modules de m\u00e9moire avanc\u00e9s con\u00e7us pour alimenter la prochaine g\u00e9n\u00e9ration d&rsquo;applications de calcul \u00e0 haute performance et d&rsquo;intelligence artificielle.<\/span><\/h3>\n<p>Le JEDEC a r\u00e9v\u00e9l\u00e9 des d\u00e9tails essentiels sur ses prochaines normes pour les modules de m\u00e9moire double en ligne \u00e0 rangs multiples DDR5 (MRDIMM) et un module de m\u00e9moire \u00e0 compression (CAMM) de nouvelle g\u00e9n\u00e9ration pour la LPDDR6. Les nouveaux MRDIMM et CAMM pour LPDDR6 sont pr\u00eats \u00e0 r\u00e9volutionner l&rsquo;industrie avec une largeur de bande et une capacit\u00e9 de m\u00e9moire in\u00e9gal\u00e9es.<\/p>\n<p><strong>Nouvelle conception de module<\/strong><\/p>\n<p>Les MRDIMM DDR5 offrent une nouvelle conception innovante et performante de module de m\u00e9moire afin d&rsquo;am\u00e9liorer les taux de transfert de donn\u00e9es et les performances globales du syst\u00e8me. Le multiplexage permet de combiner et de transmettre plusieurs signaux de donn\u00e9es sur un seul canal, ce qui augmente drastiquement la bande passante sans n\u00e9cessiter de connexions physiques suppl\u00e9mentaires, avec en plus l&rsquo;offre d&rsquo;une mise \u00e0 niveau transparente de la bande passante pour permettre aux applications de d\u00e9passer les d\u00e9bits de donn\u00e9es des modules DDR5 RDIMM.<\/p>\n<p><strong> Parmi les autres caract\u00e9ristiques pr\u00e9vues, citons<\/strong><\/p>\n<ul>\n<li>Compatibilit\u00e9 de la plateforme avec les RDIMM pour une configuration flexible de la bande passante pour l&rsquo;utilisateur final.<\/li>\n<li>Utilisation de composants DIMM DDR5 standard, y compris DRAM, facteur de forme DIMM et brochage, SPD, PMIC et TS pour faciliter l&rsquo;adoption.<\/li>\n<li>Mise \u00e0 l&rsquo;\u00e9chelle rapide des E\/S gr\u00e2ce \u00e0 la capacit\u00e9 du processus logique RCD\/DB.<\/li>\n<li>Exploiter l&rsquo;\u00e9cosyst\u00e8me LRDIMM existant pour l&rsquo;infrastructure de conception et de test.<\/li>\n<li>Prise en charge de la mise \u00e0 l&rsquo;\u00e9chelle multig\u00e9n\u00e9rationnelle vers DDR5-EOL<\/li>\n<\/ul>\n<p>La norme JEDEC MRDIMM devrait permettre de doubler la bande passante de pointe de la DRAM native, ce qui permettra aux applications de d\u00e9passer les d\u00e9bits de donn\u00e9es actuels et d&rsquo;atteindre de nouveaux niveaux de performance. Elle conserve les m\u00eames caract\u00e9ristiques de capacit\u00e9, de fiabilit\u00e9, de disponibilit\u00e9 et de facilit\u00e9 d&rsquo;entretien (RAS) que la norme JEDEC RDIMM. Le comit\u00e9 vise \u00e0 doubler la bande passante \u00e0 12,8 Gbps et \u00e0 augmenter la vitesse des connexions Le MRDIMM est pr\u00e9vu pour prendre en charge plus de deux rangs et est con\u00e7u pour utiliser des composants DIMM DDR5 standard, ce qui garantit la compatibilit\u00e9 avec les syst\u00e8mes RDIMM conventionnels.<\/p>\n<p>Des plans sont en cours pour un facteur de forme Tall MRDIMM afin d&rsquo;offrir une bande passante et une capacit\u00e9 plus \u00e9lev\u00e9es sans modifier le bo\u00eetier DRAM. Ce facteur de forme innovant et plus haut permettra de doubler le nombre de bo\u00eetiers DRAM \u00e0 puce unique mont\u00e9s sur le module DIMM sans qu&rsquo;il soit n\u00e9cessaire d&rsquo;utiliser des bo\u00eetiers 3DS.<\/p>\n<p>Dans le prolongement de la norme JEDEC JESD318 CAMM2 Memory Module, JC-45 d\u00e9veloppe un module CAMM de nouvelle g\u00e9n\u00e9ration pour LPDDR6 visant une vitesse maximale sup\u00e9rieure \u00e0 14,4 GT\/s. Comme pr\u00e9vu, le module offrira \u00e9galement un sous-canal de 24 bits, un canal de 48 bits et un r\u00e9seau de connecteurs.<\/p>\n<p>Les deux projets sont en cours de d\u00e9veloppement au sein du comit\u00e9 JC-45 du JEDEC pour les modules DRAM.<\/p>\n<p><a href=\"http:\/\/www.jedec.org\">www.jedec.org<\/a><\/p>\n<p><a href=\"https:\/\/news.google.com\/publications\/CAAqBwgKMJbcwQswuPfYAw?hl=fr&amp;gl=BE&amp;ceid=BE:fr\" target=\"news.google.com\" rel=\"noopener\">Suivre ECInews sur Google news<\/a><\/p>\n<p>&nbsp;<\/p>\n","protected":false},"excerpt":{"rendered":"<p>Les prochaines normes de m\u00e9moire DDR5 MRDIMM et LPDDR6 CAMM devraient offrir une largeur de bande et une capacit\u00e9 de m\u00e9moire in\u00e9gal\u00e9es.<\/p>\n","protected":false},"author":11,"featured_media":456662,"comment_status":"closed","ping_status":"closed","sticky":false,"template":"","format":"standard","meta":{"_acf_changed":false,"footnotes":""},"categories":[883],"tags":[3679,7092,7089,5127,7087,7090,4283,7088],"domains":[47],"ppma_author":[1143,3682],"class_list":["post-456728","post","type-post","status-publish","format-standard","has-post-thumbnail","hentry","category-technologies","tag-ai-fr","tag-boitier-3ds","tag-ddr5-mrdimm-fr","tag-hpc-fr","tag-jedec-fr","tag-lpddr6-camm-fr","tag-memoire-fr","tag-rdimm-fr","domains-electronique-eci"],"acf":[],"yoast_head":"<title>Le JEDEC d\u00e9voile de nouvelles normes de m\u00e9moire pour le HPC e...<\/title>\n<meta name=\"description\" content=\"Les prochaines normes de m\u00e9moire DDR5 MRDIMM et LPDDR6 CAMM devraient offrir une largeur de bande et une capacit\u00e9 de m\u00e9moire in\u00e9gal\u00e9es.\" \/>\n<meta name=\"robots\" content=\"index, follow, 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