{"id":449768,"date":"2024-04-27T10:54:57","date_gmt":"2024-04-27T08:54:57","guid":{"rendered":"https:\/\/www.eenewseurope.com\/?p=449768"},"modified":"2024-04-26T21:06:55","modified_gmt":"2024-04-26T19:06:55","slug":"tsmc-planifie-son-process-de-16-nm-pour-2026","status":"publish","type":"post","link":"https:\/\/www.ecinews.fr\/fr\/tsmc-planifie-son-process-de-16-nm-pour-2026\/","title":{"rendered":"TSMC planifie son process de 1,6 nm pour 2026"},"content":{"rendered":"<h3>TSMC pr\u00e9voit un processus de 1,6 nm, appel\u00e9 A16, pour une production en 2026, ainsi qu&rsquo;un substrat chiplet \u00e0 l&rsquo;\u00e9chelle du wafer et un process chiplet pour l&rsquo;automobile.<\/h3>\n<p>Le process A16 utilise l&rsquo;architecture TSMC Super Power Rail avec ses transistors nanosheet pour une production pr\u00e9vue en 2026. Il am\u00e9liore la densit\u00e9 logique et les performances en d\u00e9diant des ressources de routage c\u00f4t\u00e9 frontal aux signaux pour le calcul \u00e0 haute performance et les puces d&rsquo;intelligence artificielle avec des routes de signaux complexes et des r\u00e9seaux de distribution d&rsquo;\u00e9nergie denses. Elle s&rsquo;attaquera \u00e0 l&rsquo;architecture de puissance dorsale d&rsquo;Intel, qui est essentielle pour les n\u0153uds de processus 18A et 14A.<\/p>\n<p>Le processus TSMC A16 permettra d&rsquo;am\u00e9liorer la vitesse de 8 \u00e0 10 % \u00e0 la m\u00eame tension d&rsquo;alimentation que le processus N2P 2nm, de r\u00e9duire la consommation d&rsquo;\u00e9nergie de 15 \u00e0 20 % \u00e0 la m\u00eame vitesse et de multiplier par 1,10 la densit\u00e9 des puces.<\/p>\n<p>La prochaine technologie N2 de TSMC sera accompagn\u00e9e de TSMC NanoFlex, avec une flexibilit\u00e9 dans les cellules standard de 2 nm, les \u00e9l\u00e9ments de base de la conception des puces, avec des cellules courtes mettant l&rsquo;accent sur la petite surface et une plus grande efficacit\u00e9 \u00e9nerg\u00e9tique, et des cellules hautes maximisant les performances. Les concepteurs sont en mesure d&rsquo;optimiser la combinaison de cellules courtes et hautes au sein d&rsquo;un m\u00eame bloc de conception, en ajustant les conceptions pour atteindre des compromis optimaux en termes de puissance, de performances et de surface.<\/p>\n<ul>\n<li><a href=\"https:\/\/www.eenewseurope.com\/en\/synopsys-drives-2nm-analog-ip-photonics-with-tsmc\/\">Synopsys d\u00e9veloppe l&rsquo;IP analogique 2 nm et la photonique avec TSMC<\/a><\/li>\n<li><a href=\"https:\/\/www.eenewseurope.com\/en\/tsmc-synopsys-using-nvidias-ai-capable-culitho-for-production\/\">TSMC et Synopsys utilisent le cuLitho de Nvidia compatible avec l&rsquo;IA<\/a><\/li>\n<\/ul>\n<p>TSMC a \u00e9galement introduit sa technologie System-on-Wafer (TSMC-SoW) pour les substrats chiplets \u00e0 l&rsquo;\u00e9chelle du wafer. Cela permet de disposer d&rsquo;un grand nombre de matrices sur un wafer de 300 mm, offrant ainsi une plus grande puissance de calcul tout en occupant beaucoup moins d&rsquo;espace dans les centres de donn\u00e9es et en augmentant les performances par watt de plusieurs ordres de grandeur.<\/p>\n<p>La premi\u00e8re offre SoW, un wafer \u00e0 logique seule bas\u00e9e sur la technologie InFO (Integrated Fan-Out), est d\u00e9j\u00e0 en production et une version \u00ab\u00a0chip-on-wafer\u00a0\u00bb tirant parti de la technologie CoWoS devrait \u00eatre pr\u00eate en 2027, permettant l&rsquo;int\u00e9gration de SoIC, HBM et d&rsquo;autres composants pour cr\u00e9er un syst\u00e8me puissant au niveau du wafer avec une puissance de calcul comparable \u00e0 celle d&rsquo;un rack de serveur de centre de donn\u00e9es, voire d&rsquo;un serveur entier.<\/p>\n<p>\u00ab\u00a0Nous entrons dans un monde o\u00f9 l&rsquo;intelligence artificielle fonctionne non seulement dans les centres de donn\u00e9es, mais aussi dans les PC, les appareils mobiles, les automobiles et m\u00eame l&rsquo;Internet des objets\u00a0\u00bb, a d\u00e9clar\u00e9 le PDG de TSMC, le Dr C.C. Wei. \u00ab\u00a0Chez TSMC, nous offrons \u00e0 nos clients l&rsquo;ensemble de technologies le plus complet pour r\u00e9aliser leurs visions de l&rsquo;IA, depuis le silicium le plus avanc\u00e9 au monde jusqu&rsquo;au portefeuille le plus large de plates-formes de packaging et de circuits int\u00e9gr\u00e9s 3D avanc\u00e9s, en passant par les technologies sp\u00e9cialis\u00e9es qui int\u00e8grent le monde num\u00e9rique au monde r\u00e9el.\u00a0\u00bb<\/p>\n<ul>\n<li><a href=\"https:\/\/www.eenewseurope.com\/en\/cerebras-shows-third-generation-wafer-scale-ai-processor\/\">Cerebras pr\u00e9sente un processeur d&rsquo;IA de troisi\u00e8me g\u00e9n\u00e9ration \u00e0 l&rsquo;\u00e9chelle de la plaquette<\/a><\/li>\n<li><a href=\"https:\/\/www.eenewseurope.com\/en\/photonic-interconnect-for-wafer-scale-chips\/\">Interconnexion photonique pour les puces \u00e0 l&rsquo;\u00e9chelle de la plaquette<\/a><\/li>\n<\/ul>\n<p>TSMC a \u00e9galement annonc\u00e9 N4C, une extension de la technologie N4P avec une r\u00e9duction du co\u00fbt de la puce pouvant atteindre 8,5 % et un faible effort d&rsquo;adoption, dont la production en volume est pr\u00e9vue pour 2025. N4C offre une propri\u00e9t\u00e9 intellectuelle de base et des r\u00e8gles de conception efficaces en termes de surface qui sont enti\u00e8rement compatibles avec le N4P largement adopt\u00e9, avec un meilleur rendement gr\u00e2ce \u00e0 la r\u00e9duction de la taille de la puce, ce qui constitue une option rentable pour les produits de valeur qui migrent vers le prochain n\u0153ud technologique avanc\u00e9 de TSMC.<\/p>\n<ul>\n<li><a href=\"https:\/\/www.eenewseurope.com\/en\/sipearl-looks-to-automotive-chiplets\/\">SiPearl s&rsquo;int\u00e9resse aux puces automobiles<\/a><\/li>\n<li><a href=\"https:\/\/www.eenewseurope.com\/en\/imec-looks-to-automotive-chiplet-programme\/\">L&rsquo;imec se penche sur le programme de chiplets pour l&rsquo;automobile<\/a><\/li>\n<\/ul>\n<p>Apr\u00e8s avoir introduit le proc\u00e9d\u00e9 N3AE \u00ab\u00a0Auto Early\u00a0\u00bb en 2023, TSMC d\u00e9veloppe des proc\u00e9d\u00e9s InFO-oS et CoWoS-R chiplet pour des applications telles que les syst\u00e8mes avanc\u00e9s d&rsquo;aide \u00e0 la conduite (ADAS), le contr\u00f4le des v\u00e9hicules et les ordinateurs centraux des v\u00e9hicules. Ils viseront la qualification AEC-Q100 Grade 2 d&rsquo;ici le quatri\u00e8me trimestre 2025.<\/p>\n<p><a href=\"http:\/\/www.tsmc.com\">www.tsmc.com<\/a><\/p>\n<p>&nbsp;<\/p>\n","protected":false},"excerpt":{"rendered":"<p>TSMC pr\u00e9voit un processus de 1,6 nm, appel\u00e9 A16, pour une production en 2026, ainsi qu&rsquo;un substrat chiplet \u00e0 l&rsquo;\u00e9chelle du wafer et un process chiplet pour l&rsquo;automobile. Le process A16 utilise l&rsquo;architecture TSMC Super Power Rail avec ses transistors nanosheet pour une production pr\u00e9vue en 2026. Il am\u00e9liore la densit\u00e9 logique et les performances [&hellip;]<\/p>\n","protected":false},"author":34,"featured_media":449703,"comment_status":"closed","ping_status":"closed","sticky":false,"template":"","format":"standard","meta":{"_acf_changed":false,"footnotes":""},"categories":[883],"tags":[6246,2264,2541],"domains":[47],"ppma_author":[1153,3640],"class_list":["post-449768","post","type-post","status-publish","format-standard","has-post-thumbnail","hentry","category-technologies","tag-1-6nm-fr","tag-fabs","tag-tsmc","domains-electronique-eci"],"acf":[],"yoast_head":"<title>TSMC planifie son process de 1,6 nm pour 2026 ...<\/title>\n<meta name=\"description\" content=\"TSMC pr\u00e9voit un process A16 de 1,6 nm en 2026, ainsi qu&#039;un substrat chiplet \u00e0 l&#039;\u00e9chelle du wafer et un process chiplet pour l&#039;automobile.\" \/>\n<meta name=\"robots\" content=\"index, follow, max-snippet:-1, max-image-preview:large, max-video-preview:-1\" \/>\n<link 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