{"id":447583,"date":"2024-04-02T19:53:09","date_gmt":"2024-04-02T17:53:09","guid":{"rendered":"https:\/\/www.eenewseurope.com\/?p=447583"},"modified":"2024-04-02T19:53:09","modified_gmt":"2024-04-02T17:53:09","slug":"red-semiconductor-annonce-lextension-de-visc-a-risc-v","status":"publish","type":"post","link":"https:\/\/www.ecinews.fr\/fr\/red-semiconductor-annonce-lextension-de-visc-a-risc-v\/","title":{"rendered":"Red Semiconductor annonce l’extension de VISC \u00e0 RISC-V"},"content":{"rendered":"

La start-up anglaise , bas\u00e9e \u00e0 Oxford Red Semiconductor\u00a0 a annonc\u00e9 VISC, son architecture de jeu d’instructions bas\u00e9e sur RISC-V avec des extensions pour l’intelligence artificielle et la cryptographie.<\/span><\/h3>\n

VISC – Versatile Intrinsic Structured Computing (calcul structur\u00e9 intrins\u00e8que polyvalent), est un coeur de microprocesseur RISC-V acc\u00e9l\u00e9r\u00e9 qui prend en charge les algorithmes math\u00e9matiques pour une ex\u00e9cution parall\u00e8le dans son moteur de reconfiguration. L’entreprise affirme que VISC peut augmenter les performances math\u00e9matiques de 10 \u00e0 100 fois, tout en comprimant le code 100 fois et en s\u00e9curisant les donn\u00e9es critiques.\u00a0VISC int\u00e8gre des fonctionnalit\u00e9s telles que PUF (Physically Unclonable Function) et TRNG (True Random Number Generation) pour s\u00e9curiser les applications et la cryptographie.<\/p>\n

Le VISC est d\u00e9crit comme ayant une architecture SIMEX (Single-Issue Multi-Execute), qui rappelle les extensions de traitement parall\u00e8le de type DSP SIMD (Single-Issue-Multi-Data) offertes par les processeurs Arm.<\/p>\n

RISC-V diff\u00e9renci\u00e9<\/h4>\n

\u00ab\u00a0RISC-V a le potentiel pour devenir l’architecture de choix pour l’IA universelle, de la m\u00eame mani\u00e8re qu’Arm est devenue l’architecture des smartphones. Pour ce faire, elle a besoin d’une approche mat\u00e9rielle diff\u00e9renci\u00e9e et puissante, capable d’effectuer des calculs d’IA beaucoup plus efficacement\u00a0\u00bb, a d\u00e9clar\u00e9 James Lewis, PDG de Red Semiconductor, dans un communiqu\u00e9. Il a ajout\u00e9 : \u00a0\u00bb Red est \u00e0 l’avant-garde avec VISC, une approche bas\u00e9e sur RISC-V qui rationalise radicalement le traitement algorithmique pour fournir des solutions d’IA de pointe plus rapides, plus petites et moins consommatrices d’\u00e9nergie. VISC offre les avantages en termes de performances des acc\u00e9l\u00e9rateurs d\u00e9di\u00e9s avec la polyvalence d’un microprocesseur \u00e0 usage g\u00e9n\u00e9ral. Pour les d\u00e9veloppeurs de SoC, il permet de r\u00e9aliser de multiples fonctions de calcul h\u00e9t\u00e9rog\u00e8nes avec un jeu d’instructions et un c\u0153ur mat\u00e9riel unifi\u00e9s.\u00a0\u00bb\u00a0a d\u00e9clar\u00e9 Jon Peddie, analyste : \u00ab\u00a0VISC a le potentiel de remodeler la conception de SoC h\u00e9t\u00e9rog\u00e8nes pour des segments tels que l’Edge AI, tout comme les GPU l’ont fait sur le march\u00e9 des smartphones, en devenant un important moteur de valeur.\u00a0\u00bb<\/p>\n

La soci\u00e9t\u00e9 pr\u00e9cise que le VISC est livr\u00e9 sous forme de noyau compatible RISC-V ou d’IP pouvant \u00eatre utilis\u00e9 dans des ASIC ou des FPGA.\u00a0Les registres, les d\u00e9codeurs et le moteur d’ex\u00e9cution du VISC sont optimis\u00e9s pour le calcul parall\u00e8le de fonctions r\u00e9p\u00e9titives telles que les transform\u00e9es de Fourier rapides, les transform\u00e9es en cosinus discr\u00e8tes, les multiplications de matrices et les calculs sur les grands nombres entiers. Les applications typiques qui peuvent en b\u00e9n\u00e9ficier comprennent l’inf\u00e9rence de l’IA, l’analyse en temps r\u00e9el et le streaming vid\u00e9o.<\/p>\n

En termes de compactage du code, une multiplication matricielle VISC ne n\u00e9cessite que trois instructions, contre plus de 100 instructions pour les ISA classiques, a affirm\u00e9 M. Red. de son c\u00f4t\u00e9,\u00a0M. Lewis a indiqu\u00e9 que Red Semiconductor \u00e9tablissait des partenariats avec des soci\u00e9t\u00e9s sp\u00e9cialis\u00e9es dans le RISC-V, la cryptographie et les outils pour soutenir l’architecture VISC.<\/p>\n

www.redsemiconductor.com<\/a><\/p>\n

Suivre ECInews sur Google news<\/a><\/p>\n

\u00a0<\/h4>\n

 <\/p>\n","protected":false},"excerpt":{"rendered":"

La start-up anglaise , bas\u00e9e \u00e0 Oxford Red Semiconductor\u00a0 a annonc\u00e9 VISC, son architecture de jeu d’instructions bas\u00e9e sur RISC-V avec des extensions pour l’intelligence artificielle et la cryptographie. VISC – Versatile Intrinsic Structured Computing (calcul structur\u00e9 intrins\u00e8que polyvalent), est un coeur de microprocesseur RISC-V acc\u00e9l\u00e9r\u00e9 qui prend en charge les algorithmes math\u00e9matiques pour une […]<\/p>\n","protected":false},"author":11,"featured_media":447566,"comment_status":"closed","ping_status":"closed","sticky":false,"template":"","format":"standard","meta":{"_acf_changed":false,"footnotes":""},"categories":[883],"tags":[6105,1048,906,1674,3641],"domains":[47],"ppma_author":[1143,3631],"class_list":["post-447583","post","type-post","status-publish","format-standard","has-post-thumbnail","hentry","category-technologies","tag-cryptographie","tag-intelligence-artificielle","tag-mpus-mcus-fr","tag-risc-v-2","tag-risc-v-fr","domains-electronique-eci"],"acf":[],"yoast_head":"Red Semiconductor annonce l'extension de VISC \u00e0 RISC-V ...<\/title>\n<meta name=\"description\" content=\"VISC, son ISA bas\u00e9 sur RISC-V avec des extensions pour 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