{"id":445553,"date":"2024-03-07T09:17:46","date_gmt":"2024-03-07T08:17:46","guid":{"rendered":"https:\/\/www.eenewseurope.com\/?p=445553"},"modified":"2024-03-07T09:19:18","modified_gmt":"2024-03-07T08:19:18","slug":"intel-ajoute-lia-a-loutil-fpga-quatrus-daltera","status":"publish","type":"post","link":"https:\/\/www.ecinews.fr\/fr\/intel-ajoute-lia-a-loutil-fpga-quatrus-daltera\/","title":{"rendered":"Intel ajoute l&rsquo;IA \u00e0 l&rsquo;outil FPGA Quatrus d&rsquo;Altera"},"content":{"rendered":"<h3>Intel ajoute la prise en charge de l&rsquo;IA \u00e0 ses outils FPGA Quartus, \u00e0 l&rsquo;occasion de la scission de cette activit\u00e9 sous le nom d&rsquo;Altera.<\/h3>\n<p>\u00ab\u00a0Alors que les clients sont confront\u00e9s \u00e0 des d\u00e9fis technologiques de plus en plus complexes et s&rsquo;efforcent de se diff\u00e9rencier de leurs concurrents et d&rsquo;acc\u00e9l\u00e9rer le temps de retour sur investissement, nous avons l&rsquo;opportunit\u00e9 de revigorer le march\u00e9 des FPGA\u00a0\u00bb, a d\u00e9clar\u00e9 Sandra Rivera, PDG d&rsquo;Altera, qu&rsquo;Intel envisage de c\u00e9der au cours des deux prochaines ann\u00e9es.<\/p>\n<ul>\n<li><a href=\"https:\/\/www.eenewseurope.com\/en\/intel-completes-altera-acquisition\/\">Intel finalise l&rsquo;acquisition d&rsquo;Altera<\/a><\/li>\n<li><a href=\"https:\/\/www.eenewseurope.com\/en\/altera-design-software-release-adds-support-for-dsp-fpu-blocks\/\">La nouvelle version du logiciel de conception d&rsquo;Altera prend en charge les DSP <\/a><\/li>\n<\/ul>\n<p>Quartus a \u00e9t\u00e9 d\u00e9velopp\u00e9 par Altera pour r\u00e9pondre \u00e0 la complexit\u00e9 de la conception des FPGA et a ajout\u00e9 la capacit\u00e9 DSP en 2014 avant l&rsquo;acquisition par Intel. Intel ajoute des capacit\u00e9s d&rsquo;IA faciles \u00e0 int\u00e9grer afin de tirer parti de la croissance rapide du march\u00e9 de l&rsquo;IA, en particulier pour l&rsquo;Agilex 5, dont les blocs DSP ont \u00e9t\u00e9 am\u00e9lior\u00e9s pour prendre en charge les calculs Tensor de l&rsquo;IA.<\/p>\n<p>La mise \u00e0 jour de Quartus inclut la FPGA AI Suite et OpenVINO, qui g\u00e9n\u00e8rent une propri\u00e9t\u00e9 intellectuelle (IP) optimis\u00e9e bas\u00e9e sur des frameworks standards tels que TensorFlow et Pytorch.<\/p>\n<blockquote class=\"wp-embedded-content\" data-secret=\"1narRfUxuY\"><p><a href=\"https:\/\/www.eenewseurope.com\/en\/intel-plans-to-ipo-its-fpga-business\/\">Intel plans to IPO its FPGA business<\/a><\/p><\/blockquote>\n<p><iframe class=\"wp-embedded-content lazyload\" sandbox=\"allow-scripts\" security=\"restricted\" style=\"position: absolute; visibility: hidden;\" title=\"&#8220;Intel plans to IPO its FPGA business&#8221; &#8212; eeNews Europe\" data-src=\"https:\/\/www.eenewseurope.com\/en\/intel-plans-to-ipo-its-fpga-business\/embed\/#?secret=RWfTkWuOoP#?secret=1narRfUxuY\" data-secret=\"1narRfUxuY\" width=\"500\" height=\"282\" frameborder=\"0\" marginwidth=\"0\" marginheight=\"0\" scrolling=\"no\" src=\"data:image\/svg+xml;base64,PHN2ZyB3aWR0aD0iMSIgaGVpZ2h0PSIxIiB4bWxucz0iaHR0cDovL3d3dy53My5vcmcvMjAwMC9zdmciPjwvc3ZnPg==\" data-load-mode=\"1\"><\/iframe><\/p>\n<p>Les FPGA Agilex 5 sont construits dans un process de 7nm et sont maintenant en production de masse. Il s&rsquo;agit \u00e9galement du premier syst\u00e8me de processeur d&rsquo;application \u00ab\u00a0asym\u00e9trique\u00a0\u00bb dot\u00e9 d&rsquo;un processeur ARM Cortex-A76 \u00e0 double c\u0153ur et d&rsquo;un processeur ARM Cortex-A55 \u00e0 double c\u0153ur sur une puce monolithique. Contrairement aux FPGA AMD\/Xilinx qui utilisent des chiplets d&rsquo;acc\u00e9l\u00e9ration de l&rsquo;IA distincts.<\/p>\n<p>L&rsquo;Agilex 5 comprend des \u00e9metteurs-r\u00e9cepteurs GTS \u00e0 grande vitesse jusqu&rsquo;\u00e0 28,1 Gbit\/s et un support PCI Express 4.0 \u00d78, ainsi qu&rsquo;une interface de m\u00e9moire externe DDR5 jusqu&rsquo;\u00e0 4 000 Mbit\/s.<\/p>\n<p>Les FPGA Agilex 9 sont \u00e9galement maintenant produits en volume avec des convertisseurs de donn\u00e9es \u00e0 grande vitesse pour des applications radar et militaires-a\u00e9rospatiales qui n\u00e9cessitent des FPGA \u00e0 signaux mixtes \u00e0 large bande passante.<\/p>\n<p>Les composants Agilex 7 F-series et I-series sont mis en production afin d&rsquo;am\u00e9liorer la performance par watt des centres de donn\u00e9es, des r\u00e9seaux et des applications de d\u00e9fense. Ils utilisent le chiplet R-Tile pour ajouter des capacit\u00e9s PCIe 5.0 et CXL et c&rsquo;est le seul FPGA avec une propri\u00e9t\u00e9 intellectuelle (IP) supportant ces interfaces.<\/p>\n<p>Agilex 3 est con\u00e7u comme une gamme de FPGA \u00e0 faible consommation d&rsquo;\u00e9nergie et \u00e0 valeur ajout\u00e9e pour des fonctions peu complexes destin\u00e9es aux applications de cloud, de communication et edge intelligente.<\/p>\n<p><a href=\"http:\/\/www.altera.com\">www.altera.com<\/a><\/p>\n<p>&nbsp;<\/p>\n","protected":false},"excerpt":{"rendered":"<p>Intel ajoute la prise en charge de l&rsquo;IA \u00e0 ses outils FPGA Quartus, \u00e0 l&rsquo;occasion de la scission de cette activit\u00e9 sous le nom d&rsquo;Altera. \u00ab\u00a0Alors que les clients sont confront\u00e9s \u00e0 des d\u00e9fis technologiques de plus en plus complexes et s&rsquo;efforcent de se diff\u00e9rencier de leurs concurrents et d&rsquo;acc\u00e9l\u00e9rer le temps de retour sur [&hellip;]<\/p>\n","protected":false},"author":34,"featured_media":445254,"comment_status":"closed","ping_status":"closed","sticky":false,"template":"","format":"standard","meta":{"_acf_changed":false,"footnotes":""},"categories":[880],"tags":[3679,5969,2198,908,917],"domains":[47],"ppma_author":[1153,3640],"class_list":["post-445553","post","type-post","status-publish","format-standard","has-post-thumbnail","hentry","category-actualites-economiques","tag-ai-fr","tag-altera","tag-ia","tag-plds-fpgas-asics-fr","tag-software-embedded-tools-fr","domains-electronique-eci"],"acf":[],"yoast_head":"<title>Intel ajoute l&#039;IA \u00e0 l&#039;outil FPGA Quatrus d&#039;Altera ...<\/title>\n<meta name=\"description\" content=\"Intel ajoute la prise en charge de l&#039;IA \u00e0 ses outils FPGA Quartus, dans le cadre de la scission d&#039;Altera, et ajoute lTensor \u00e0 ses DSP.\" \/>\n<meta name=\"robots\" content=\"index, follow, max-snippet:-1, max-image-preview:large, max-video-preview:-1\" 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