{"id":442906,"date":"2024-02-05T08:21:03","date_gmt":"2024-02-05T07:21:03","guid":{"rendered":"https:\/\/www.eenewseurope.com\/?p=442906"},"modified":"2024-02-04T18:31:48","modified_gmt":"2024-02-04T17:31:48","slug":"version-6-pour-les-asic-a-faible-cout-de-tiny-tapeout","status":"publish","type":"post","link":"https:\/\/www.ecinews.fr\/fr\/version-6-pour-les-asic-a-faible-cout-de-tiny-tapeout\/","title":{"rendered":"Version 6 pour les ASIC \u00e0 faible co\u00fbt de Tiny Tapeout"},"content":{"rendered":"<h3>Le projet d&rsquo;ASIC \u00e0 faible co\u00fbt Tiny Tapeout 6 est ouvert aux soumissions. Il ajoute la gestion de l&rsquo;alimentation pour toutes les conceptions, la prise en charge des signaux mixtes et des broches analogiques.<\/h3>\n<p>Le Tiny Tapeout 6 a le m\u00eame espace, les m\u00eames entr\u00e9es-sorties et la m\u00eame vitesse que le pr\u00e9c\u00e9dent Tiny Tapeout 5, mais le power gating ouvre d&rsquo;autres flux de conception et les soumissions se terminent le 19 avril. Le projet combine des centaines de conceptions ASIC provenant de chercheurs et de d\u00e9veloppeurs sur une seule puce fabriqu\u00e9e par Skywater selon un proc\u00e9d\u00e9 de 130 nm, qui est ensuite mont\u00e9e sur une carte.<\/p>\n<p>\u00ab\u00a0Maintenant que toutes les conceptions peuvent \u00eatre g\u00e9r\u00e9es par l&rsquo;alimentation, nous acceptons les conceptions analogiques, les signaux mixtes et les soumissions r\u00e9alis\u00e9es avec d&rsquo;autres flux ou outils propri\u00e9taires. Tant que votre conception respecte les r\u00e8gles DRC du Sky130, vous \u00eates accept\u00e9\u00a0\u00bb, a d\u00e9clar\u00e9 Matt Venn, l&rsquo;organisateur du projet. \u00ab\u00a0Si vous souhaitez des broches d&rsquo;E\/S analogiques, le prix est de 40 $ chacune, et votre projet doit utiliser un minimum de 2 tuiles. Le mux analogique est encore en cours de d\u00e9veloppement et nous pr\u00e9voyons d&rsquo;accepter les conceptions n\u00e9cessitant des broches d&rsquo;E\/S analogiques d&rsquo;ici le d\u00e9but du mois de mars.\u00a0\u00bb<\/p>\n<ul>\n<li><a href=\"https:\/\/www.eenewseurope.com\/en\/tinytapeout-boost-for-open-source-silicon-chip-design\/\">Des co\u00fbts r\u00e9duits pour la conception de puces en silicium \u00e0 source ouverte <\/a><\/li>\n<li><a href=\"https:\/\/www.eenewseurope.com\/en\/tiny-tapeout-5-opens-for-submissions\/\">Ouverture des soumissions pour le Tiny Tapeout 5<\/a><\/li>\n<\/ul>\n<p>Les r\u00e9sultats des conceptions sur une s\u00e9rie de wafers multiprojets sont attendus pour octobre 2024 et la livraison aux concepteurs pour d\u00e9cembre 2024. Cependant, la pand\u00e9mie de Covid-19 et les faibles co\u00fbts de production ont eu pour cons\u00e9quence que les projets TT02 n&rsquo;ont commenc\u00e9 \u00e0 \u00eatre exp\u00e9di\u00e9s qu&rsquo;apr\u00e8s avoir \u00e9t\u00e9 test\u00e9s.<\/p>\n<p>Le prix des wafers multi-projets a \u00e9galement augment\u00e9.<\/p>\n<p>\u00ab\u00a0Lorsque nous avons eu l&rsquo;id\u00e9e et la structure de prix de TinyTapeout, le service Efabless chipIgnite proposait 300 puces WLCSP pour 10 000 dollars. Peu de temps apr\u00e8s, l&#8217;emballage a \u00e9t\u00e9 remplac\u00e9 par le type QFN, plus co\u00fbteux, et la quantit\u00e9 a \u00e9t\u00e9 ramen\u00e9e \u00e0 100\u00a0\u00bb, a d\u00e9clar\u00e9 M. Venn.<\/p>\n<p>\u00ab\u00a0Avec le triplement du prix des puces, nous avons d\u00fb augmenter le prix du mat\u00e9riel pour assurer la viabilit\u00e9 de l&rsquo;entreprise. La bonne nouvelle, c&rsquo;est qu&rsquo;<a href=\"https:\/\/zerotoasiccourse.us7.list-manage.com\/track\/click?u=5d5a474f6c30e153ec17de7b5&amp;id=18710defa8&amp;e=0a652e9231\">Efabless<\/a> nous sponsorise toujours, donc les 100 premi\u00e8res soumissions de particuliers n&rsquo;augmentent que de 50 $, soit 150 $ pour 1 tuile, l&rsquo;ASIC et la carte de d\u00e9monstration.<br \/>\nPour les entreprises, les universit\u00e9s et les particuliers, apr\u00e8s les 100 premi\u00e8res ventes, le nouveau prix est de 300 dollars pour une tuile, l&rsquo;ASIC et la carte de d\u00e9monstration. Si vous avez besoin de plus d&rsquo;espace, les tuiles suppl\u00e9mentaires restent au prix de 50 dollars\u00a0\u00bb, a-t-il d\u00e9clar\u00e9.<\/p>\n<p>Le r\u00e9cent projet TT05 a fait l&rsquo;objet de 174 soumissions, utilisant 75 % de l&rsquo;espace disponible, contre 160 pour TT02. Les conceptions du TT05 comprennent un processeur RISC-V compatible avec Linux, un r\u00e9seau neuronal programmable, un g\u00e9n\u00e9rateur de sons \u00e0 table d&rsquo;ondes et une exp\u00e9rience de m\u00e9tastabilit\u00e9.<\/p>\n<p>Une nouvelle <a href=\"https:\/\/zerotoasiccourse.us7.list-manage.com\/track\/click?u=5d5a474f6c30e153ec17de7b5&amp;id=bfd6533cc1&amp;e=0a652e9231\">carte interactive des diff\u00e9rents projets est disponible ici<\/a>.<\/p>\n<p><a href=\"http:\/\/www.tinytapeout.com\">www.tinytapeout.com<\/a><\/p>\n","protected":false},"excerpt":{"rendered":"<p>Le projet d&rsquo;ASIC \u00e0 faible co\u00fbt Tiny Tapeout 6 est ouvert aux soumissions. Il ajoute la gestion de l&rsquo;alimentation pour toutes les conceptions, la prise en charge des signaux mixtes et des broches analogiques. Le Tiny Tapeout 6 a le m\u00eame espace, les m\u00eames entr\u00e9es-sorties et la m\u00eame vitesse que le pr\u00e9c\u00e9dent Tiny Tapeout 5, [&hellip;]<\/p>\n","protected":false},"author":34,"featured_media":442873,"comment_status":"closed","ping_status":"closed","sticky":false,"template":"","format":"standard","meta":{"_acf_changed":false,"footnotes":""},"categories":[880],"tags":[908,5763],"domains":[47],"ppma_author":[1153,3640],"class_list":["post-442906","post","type-post","status-publish","format-standard","has-post-thumbnail","hentry","category-actualites-economiques","tag-plds-fpgas-asics-fr","tag-tiny-tapeout","domains-electronique-eci"],"acf":[],"yoast_head":"<title>Version 6 pour les ASIC \u00e0 faible co\u00fbt de Tiny Tapeout ...<\/title>\n<meta name=\"description\" content=\"Le projet d&#039;ASIC \u00e0 faible co\u00fbt Tiny Tapeout 6 est ouvert aux soumissions. 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