{"id":424734,"date":"2023-06-19T18:02:39","date_gmt":"2023-06-19T16:02:39","guid":{"rendered":"https:\/\/www.eenewseurope.com\/?p=424734"},"modified":"2023-06-19T18:02:39","modified_gmt":"2023-06-19T16:02:39","slug":"intel-et-le-cea-leti-developpent-des-materiaux-2d-pour-les-futurs-transistors","status":"publish","type":"post","link":"https:\/\/www.ecinews.fr\/fr\/intel-et-le-cea-leti-developpent-des-materiaux-2d-pour-les-futurs-transistors\/","title":{"rendered":"Intel et le CEA-Leti d\u00e9veloppent des mat\u00e9riaux 2D pour les futurs transistors"},"content":{"rendered":"

Le g\u00e9ant des puces \u00e9lectroniques Intel et l’institut de recherche fran\u00e7ais CEA-Leti, bas\u00e9 \u00e0 Grenoble, ont d\u00e9clar\u00e9 qu’ils allaient collaborer pour d\u00e9velopper des technologies de transistors bas\u00e9es sur des dichalcog\u00e9nures bidimensionnels de m\u00e9taux de transition (TMD).<\/h2>\n

Ces mat\u00e9riaux – tels que les TMD \u00e0 base de molybd\u00e8ne et de tungst\u00e8ne – sont d\u00e9crits comme des options prometteuses pour les mat\u00e9riaux de canal pour les transistors \u00e0 \u00e9chelle r\u00e9duite. Le CEA-Leti et Intel ont cr\u00e9\u00e9 un projet de recherche commun pluriannuel pour d\u00e9velopper la technologie de transfert de couches de dichalcog\u00e9nures bidimensionnels de m\u00e9taux de transition (2D TMD) sur des wafers de 300 mm. Ces technologies pourraient \u00eatre utiles pour les process de fabrication sub-nanom\u00e9triques d\u00e9ploy\u00e9s au-del\u00e0 de 2030, a d\u00e9clar\u00e9 le CEA-Leti.<\/p>\n

Les semiconducteurs en couches 2D offrent une \u00e9paisseur inn\u00e9e de canal de transistor inf\u00e9rieure au nanom\u00e8tre, ce qui les rend appropri\u00e9s pour les plates-formes \u00e0 haute performance et \u00e0 faible consommation d’\u00e9nergie en raison de leur bon transport de porteurs et de leur mobilit\u00e9, m\u00eame pour les couches atomiquement fines. En outre, l’\u00e9paisseur du corps du composant et la bande interdite \u00e9nerg\u00e9tique mod\u00e9r\u00e9e permettent d’am\u00e9liorer le contr\u00f4le \u00e9lectrostatique et, par cons\u00e9quent, de r\u00e9duire les courants \u00e0 l’\u00e9tat bloqu\u00e9.<\/p>\n

Ces caract\u00e9ristiques font des dispositifs \u00e0 transistors 2D-FET empil\u00e9s une solution prometteuse pour la mise \u00e0 l’\u00e9chelle des transistors au-del\u00e0 de 2030, a d\u00e9clar\u00e9 le CEA-Leti. Toutefois, cela n\u00e9cessitera des m\u00e9thodes pour la croissance des canaux 2D et le transfert vers la technologie des wafers de silicium.<\/p>\n

L’objectif du projet est de cr\u00e9er un process viable pour la croissance de mat\u00e9riaux 2D de haute qualit\u00e9 sur des substrats de 300 mm et leur transfert vers un autre substrat de composants pour l’int\u00e9gration du processus du transistor.<\/p>\n

Repousser la loi de Moore<\/h4>\n

\u00ab\u00a0Alors que nous repoussons sans cesse la loi de Moore, le mat\u00e9riau 2D TMD est une option prometteuse pour repousser les limites de la mise \u00e0 l’\u00e9chelle des transistors \u00e0 l’avenir\u00a0\u00bb, a d\u00e9clar\u00e9 Robert Chau, senior fellow d’Intel pour le d\u00e9veloppement technologique, dans un communiqu\u00e9 publi\u00e9 par le CEA-Leti.<\/p>\n

M. Chau a quitt\u00e9 les \u00c9tats-Unis pour s’installer en Europe en 2022 afin de diriger la recherche europ\u00e9enne d’Intel et de piloter la R&D d’Intel avec ses partenaires sur le continent.<\/p>\n

S\u00e9bastien Dauv\u00e9, PDG du CEA-Leti, a d\u00e9clar\u00e9 qu’en raison de la temp\u00e9rature de croissance \u00e9lev\u00e9e des mat\u00e9riaux, qui d\u00e9passe 700 degr\u00e9s C, il est difficile de d\u00e9poser des empilements sous forme de couches minces et que le transfert de couches est le plus prometteur pour les int\u00e9grer dans de futurs composants.<\/p>\n

Liens et articles connexes :<\/h4>\n

www.leti-cea.com<\/a><\/p>\n

www.cea.fr<\/a><\/p>\n

www.intel.com<\/a><\/p>\n

Articles de presse :<\/h4>\n

Un alliage de germanium et d’\u00e9tain pour les futurs transistors<\/a><\/p>\n

Des transistors \u00ab\u00a0en croissance\u00a0\u00bb sur les puces \u00e9lectroniques<\/a><\/p>\n

L’IMEC pr\u00e9sente un CFET monolithique lors d’un symposium VLSI<\/a><\/p>\n

La feuille de route de l’IMEC pour les semi-conducteurs montre la fin de la mise \u00e0 l’\u00e9chelle des pas de m\u00e9tal<\/a><\/p>\n

Selon l’IMEC, l’empilement de CMOS pourrait permettre de surmonter les limites de la feuille de fourchette.<\/a><\/p>\n","protected":false},"excerpt":{"rendered":"

Le g\u00e9ant des puces \u00e9lectroniques Intel et l’institut de recherche fran\u00e7ais CEA-Leti, bas\u00e9 \u00e0 Grenoble, ont d\u00e9clar\u00e9 qu’ils allaient collaborer pour d\u00e9velopper des technologies de transistors bas\u00e9es sur des dichalcog\u00e9nures bidimensionnels de m\u00e9taux de transition (TMD). Ces mat\u00e9riaux – tels que les TMD \u00e0 base de molybd\u00e8ne et de tungst\u00e8ne – sont d\u00e9crits comme des […]<\/p>\n","protected":false},"author":34,"featured_media":424725,"comment_status":"closed","ping_status":"closed","sticky":false,"template":"","format":"standard","meta":{"_acf_changed":false,"footnotes":""},"categories":[883],"tags":[3811,3810,1103],"domains":[47],"ppma_author":[1153,3631],"class_list":["post-424734","post","type-post","status-publish","format-standard","has-post-thumbnail","hentry","category-technologies","tag-2d-fr","tag-tmd-fr","tag-transistor","domains-electronique-eci"],"acf":[],"yoast_head":"Intel et le CEA-Leti d\u00e9veloppent des mat\u00e9riaux 2D pour transi...<\/title>\n<meta name=\"description\" content=\"Intel et le CEA-Leti d\u00e9veloppent des technologies de transistors bas\u00e9es sur des dichalcog\u00e9nures 2D de m\u00e9taux de transition (TMD).\" \/>\n<meta name=\"robots\" content=\"index, follow, max-snippet:-1, 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