{"id":423023,"date":"2023-05-30T09:56:32","date_gmt":"2023-05-30T07:56:32","guid":{"rendered":"https:\/\/www.eenewseurope.com\/?p=423023"},"modified":"2023-05-30T09:56:51","modified_gmt":"2023-05-30T07:56:51","slug":"arm-lance-lip-de-coeur-de-processeur-cortex-x4","status":"publish","type":"post","link":"https:\/\/www.ecinews.fr\/fr\/arm-lance-lip-de-coeur-de-processeur-cortex-x4\/","title":{"rendered":"ARM lance l&rsquo;IP de c\u0153ur de processeur Cortex-X4"},"content":{"rendered":"<h4><span class=\"HwtZe\" lang=\"fr\"><span class=\"jCAhz ChMk0b\"><span class=\"ryNqvb\">ARM a lanc\u00e9 sa nouvelle plateforme \u00ab\u00a0Total Compute Solution\u00a0\u00bb (TCS) avec son c\u0153ur de processeur le plus rapide jamais cr\u00e9\u00e9, le X4 et un syst\u00e8me de gestion de c\u0153ur pour une fabrication sur le process 3 nm de TSMC et le process 18A d&rsquo;Intel.<\/span><\/span><\/span><\/h4>\n<p><span class=\"HwtZe\" lang=\"fr\">\u00a0<span class=\"jCAhz ChMk0b\"><span class=\"ryNqvb\">Cela peut contribuer \u00e0 r\u00e9soudre la confusion apparue r\u00e9cemment sur l&rsquo;ambition d&rsquo;ARM de fabriquer ses propres puces, ( voir <\/span><\/span><\/span><a title=\"Un prototype de CPU Arm soul\u00e8ve des questions sur le mod\u00e8le \u00e9conomique\" href=\"https:\/\/www.ecinews.fr\/fr\/un-prototype-de-cpu-arm-souleve-des-questions-sur-le-modele-economique\/\" target=\"_blank\" rel=\"noopener\">Un prototype de CPU Arm soul\u00e8ve des questions sur le mod\u00e8le \u00e9conomique) <\/a><span class=\"HwtZe\" lang=\"fr\"><span class=\"jCAhz ChMk0b\"><span class=\"ryNqvb\">car TCS comprend tous les \u00e9l\u00e9ments et sous-syst\u00e8mes qui seraient n\u00e9cessaires pour produire une puce.<\/span><\/span> <span class=\"jCAhz ChMk0b\"><span class=\"ryNqvb\">L&rsquo;IP\u00a0 (propri\u00e9t\u00e9 intellectuelle) doit encore \u00eatre prouv\u00e9e dans le silicium, et la livraison d&rsquo;un prototype de \u00ab\u00a0puce\u00a0\u00bb est un \u00e9l\u00e9ment cl\u00e9 du processus de d\u00e9veloppement.<\/span><\/span> <span class=\"jCAhz ChMk0b\"><span class=\"ryNqvb\">Ceci est particuli\u00e8rement important car la derni\u00e8re version, TCS23, est destin\u00e9e aux puces produites par le processus N3E 3nm de TSMC et le 18A d&rsquo;Intel.<\/span><\/span><\/span><\/p>\n<blockquote class=\"wp-embedded-content\" data-secret=\"0kHVHIx6Ra\"><p><a href=\"https:\/\/www.ecinews.fr\/fr\/intel-deplace-les-coeurs-arm-vers-son-process-de-18-nm-pour-la-fonderie\/\">Intel d\u00e9place les c\u0153urs ARM vers son process de 1,8 nm pour la fonderie<\/a><\/p><\/blockquote>\n<p><iframe class=\"wp-embedded-content lazyload\" sandbox=\"allow-scripts\" security=\"restricted\" style=\"position: absolute; visibility: hidden;\" title=\"\u00ab\u00a0Intel d\u00e9place les c\u0153urs ARM vers son process de 1,8 nm pour la fonderie\u00a0\u00bb &#8212; EENewsEurope\" data-src=\"https:\/\/www.ecinews.fr\/fr\/intel-deplace-les-coeurs-arm-vers-son-process-de-18-nm-pour-la-fonderie\/embed\/#?secret=1RfMbqTZlp#?secret=0kHVHIx6Ra\" data-secret=\"0kHVHIx6Ra\" width=\"500\" height=\"282\" frameborder=\"0\" marginwidth=\"0\" marginheight=\"0\" scrolling=\"no\" src=\"data:image\/svg+xml;base64,PHN2ZyB3aWR0aD0iMSIgaGVpZ2h0PSIxIiB4bWxucz0iaHR0cDovL3d3dy53My5vcmcvMjAwMC9zdmciPjwvc3ZnPg==\" data-load-mode=\"1\"><\/iframe><\/p>\n<p>&nbsp;<\/p>\n<p><span class=\"HwtZe\" lang=\"fr\"><span class=\"jCAhz ChMk0b\"><span class=\"ryNqvb\">En plus du noyau X4 avec une augmentation de 15% des performances par rapport au X3, le TCS23 comprend une unit\u00e9 syst\u00e8me DynamiQ mise \u00e0 jour, ou DSU, qui est sans doute plus importante.<\/span><\/span> <span class=\"jCAhz ChMk0b\"><span class=\"ryNqvb\">Le DSU120 prend en charge jusqu&rsquo;\u00e0 14 c\u0153urs dans un sous-syst\u00e8me avec gestion de l&rsquo;alimentation et des performances et jusqu&rsquo;\u00e0 32 Mbits de cache L3.<\/span><\/span> <\/span><\/p>\n<p><span class=\"HwtZe\" lang=\"fr\"><span class=\"jCAhz ChMk0b\"><span class=\"ryNqvb\">Le DSU peut g\u00e9rer dix c\u0153urs X4 avec quatre A720 pour les puces d&rsquo;ordinateurs portables, ainsi qu&rsquo;un cluster de processeurs \u00e0 huit c\u0153urs avec un Cortex-X4, cinq Cortex-A720 et deux Cortex-A520 pour plus de puces IA Edge IoT.<\/span><\/span> <span class=\"jCAhz ChMk0b\"><span class=\"ryNqvb\">Les puces pour ordinateurs portables sont un sujet de discussion cl\u00e9 avec le principal licenci\u00e9 Qualcomm qui d\u00e9veloppe les siens.<\/span><\/span><\/span><\/p>\n<ul>\n<li><a href=\"https:\/\/www.eenewseurope.com\/en\/qualcomm-hits-back-at-arm-over-lawsuit\/\">Qualcomm hits back at ARM over lawsuit<\/a><\/li>\n<\/ul>\n<p><span class=\"HwtZe\" lang=\"fr\"><span class=\"jCAhz ChMk0b\"><span class=\"ryNqvb\">Le DSU permet \u00e9galement un c\u0153ur X4 \u00e0 hautes performances aux c\u00f4t\u00e9s de quatre c\u0153urs A520, \u00e9galement nouveaux, et de quatre c\u0153urs A720 pour une architecture big.LITTLE plus sophistiqu\u00e9e dans les smartphones haut de gamme.<\/span><\/span> <span class=\"jCAhz ChMk0b\"><span class=\"ryNqvb\">Mediatek \u00e0 Ta\u00efwan est le principal d\u00e9veloppeur de puces bas\u00e9es sur XA et a \u00e9galement \u00e9t\u00e9 l&rsquo;un des premiers \u00e0 s&rsquo;inscrire au service de fonderie d&rsquo;Intel.<\/span><\/span> <\/span><\/p>\n<p><span class=\"HwtZe\" lang=\"fr\"><span class=\"jCAhz ChMk0b\"><span class=\"ryNqvb\">\u00ab\u00a0L&rsquo;IP 2023 innovante d&rsquo;ARM, le Cortex-X4 et le Cortex-A720, et l&rsquo;Immortalis G720 ont fourni une excellente base pour notre puce de smartphone 5G Dimensity de nouvelle g\u00e9n\u00e9ration.\u00a0\u00bb<\/span><\/span> <span class=\"jCAhz ChMk0b\"><span class=\"ryNqvb\">a d\u00e9clar\u00e9 le Dr JC Hsu, vice-pr\u00e9sident principal et directeur g\u00e9n\u00e9ral de l&rsquo;unit\u00e9 commerciale des communications sans fil de MediaTek.<\/span><\/span> <\/span><\/p>\n<p><span class=\"HwtZe\" lang=\"fr\"><span class=\"jCAhz ChMk0b\"><span class=\"ryNqvb\">\u00ab La combinaison de la technologie de pointe Intel 18A avec le c\u0153ur de processeur le plus r\u00e9cent et le plus puissant d&rsquo;ARM, le Cortex-X4, cr\u00e9era des opportunit\u00e9s pour les entreprises qui cherchent \u00e0 concevoir la prochaine g\u00e9n\u00e9ration de SoC mobiles innovants.<\/span><\/span> <span class=\"jCAhz ChMk0b\"><span class=\"ryNqvb\">ARM est un partenaire essentiel alors que nous travaillons \u00e0 la cr\u00e9ation d&rsquo;un \u00e9cosyst\u00e8me de fonderie complet pour nos clients du monde entier\u00bb, a d\u00e9clar\u00e9 Stuart Pann, vice-pr\u00e9sident corporate et directeur g\u00e9n\u00e9ral d&rsquo;Intel Foundry Services (IFS).<\/span><\/span><\/span><\/p>\n<ul>\n<li><a href=\"https:\/\/www.eenewseurope.com\/en\/arm-silicon-catalyst-team-for-ip-giveaway\/\">ARM, Silicon Catalyst team for IP giveaway<\/a><\/li>\n<li><a href=\"https:\/\/www.eenewseurope.com\/en\/analysis-arm-reshuffle-preps-for-ipo\/\">Analysis: ARM reshuffle preps for IPO<\/a><\/li>\n<\/ul>\n<p>&nbsp;<\/p>\n<p><span class=\"HwtZe\" lang=\"fr\"><span class=\"jCAhz ChMk0b\"><span class=\"ryNqvb\">Ceux-ci sont tous construits sur l&rsquo;architecture Armv9.2, qui, aux c\u00f4t\u00e9s de l&rsquo;extension Memory Tagging Extension (MTE) pour la s\u00e9curit\u00e9 du syst\u00e8me d&rsquo;exploitation Android 64 bits et SVE2 pour plus de performances logicielles, ajoute un nouvel algorithme QARMA3 pour l&rsquo;authentification par pointeur (PAC) pour supprimer les goulots d&rsquo;\u00e9tranglement de la m\u00e9moire avec s\u00e9curit\u00e9.<\/span><\/span> <\/span><\/p>\n<p><span class=\"HwtZe\" lang=\"fr\"><span class=\"jCAhz ChMk0b\"><span class=\"ryNqvb\">Cela fonctionne avec l&rsquo;authentification de pointeur (PAC) et l&rsquo;identification de cible de branche (BTI) pour am\u00e9liorer l&rsquo;int\u00e9grit\u00e9 du flux de contr\u00f4le en \u00e9liminant presque toutes les vuln\u00e9rabilit\u00e9s de programmation orient\u00e9e saut (JOP) et de programmation orient\u00e9e retour (ROP) avec des pertes de performances n\u00e9gligeables pour les processeurs X4 et A720.<\/span><\/span> <span class=\"jCAhz ChMk0b\"><span class=\"ryNqvb\">Les am\u00e9liorations du PAC, y compris le nouvel algorithme QARMA3, r\u00e9duisent l&rsquo;impact sur les performances du PAC et du BTI \u00e0 moins d&rsquo;un pour cent pour les c\u0153urs de processeur A520.<\/span><\/span><\/span><\/p>\n<p><span class=\"HwtZe\" lang=\"fr\"><span class=\"jCAhz ChMk0b\"><span class=\"ryNqvb\">\u00ab\u00a0TCS23 fournit un package complet de la derni\u00e8re IP con\u00e7ue et optimis\u00e9e pour des charges de travail sp\u00e9cifiques afin de fonctionner ensemble de mani\u00e8re transparente en tant que syst\u00e8me complet\u00a0\u00bb, a d\u00e9clar\u00e9 Chris Bergey, vice-pr\u00e9sident senior et directeur g\u00e9n\u00e9ral, Client Line of Business chez ARM.<\/span><\/span> <span class=\"jCAhz ChMk0b\"><span class=\"ryNqvb\">Le TCS23 comprend \u00e9galement un nouveau GPU Immortalis-G720 bas\u00e9 sur l&rsquo;architecture GPU de cinqui\u00e8me g\u00e9n\u00e9ration d&rsquo;ARM.<\/span><\/span> <span class=\"jCAhz ChMk0b\"><span class=\"ryNqvb\">Cela utilise Deferred Vertex Shading (DVS), une nouvelle fonctionnalit\u00e9 graphique, pour s&rsquo;adapter \u00e0 un plus grand nombre de c\u0153urs et \u00e0 des points de performance plus \u00e9lev\u00e9s.<\/span><\/span> <\/span><\/p>\n<p><span class=\"HwtZe\" lang=\"fr\"><span class=\"jCAhz ChMk0b\"><span class=\"ryNqvb\">TCS23 est pris en charge par les outils compatibles avec l&rsquo;IA de Synopsys.<\/span><\/span> <span class=\"jCAhz ChMk0b\"><span class=\"ryNqvb\">Il s&rsquo;agit notamment de la suite EDA Synopsys.ai full-stack bas\u00e9e sur l&rsquo;IA, qui exploite la puissance de l&rsquo;IA depuis l&rsquo;architecture du syst\u00e8me jusqu&rsquo;\u00e0 la fabrication pour optimiser la puissance, les performances et la surface (PPA) et am\u00e9liorer les d\u00e9lais de mise sur le march\u00e9.<\/span><\/span><\/span><\/p>\n<p><span class=\"HwtZe\" lang=\"fr\"><span class=\"jCAhz ChMk0b\"><span class=\"ryNqvb\">La famille Synopsys Verification inclut la prise en charge des processeurs Cortex-X4, Cortex-A720 et Cortex-A520 et des GPU Immortalis-G720 et Mali-G720.<\/span><\/span> <span class=\"jCAhz ChMk0b\"><span class=\"ryNqvb\">Les premiers utilisateurs de TCS23 utilisent des prototypes virtuels Synopsys avec des mod\u00e8les ARM Fast Models, une v\u00e9rification assist\u00e9e par mat\u00e9riel Synopsys et une IP de v\u00e9rification pour la derni\u00e8re interconnexion AMBA.<\/span><\/span> <\/span><\/p>\n<p><span class=\"HwtZe\" lang=\"fr\"><span class=\"jCAhz ChMk0b\"><span class=\"ryNqvb\">Synopsys dispose \u00e9galement d&rsquo;une IP d&rsquo;interface et de s\u00e9curit\u00e9 pour PCI Express 6.0 avec Integrity and Data Encryption (IDE), CXL 3.0 avec IDE, DDR5 avec Inline Memory Encryption (IME) et UCIe, qui sont tous optimis\u00e9s pour les performances avec des fonctionnalit\u00e9s sp\u00e9cifiques \u00e0 ARM et pour<\/span><\/span> <span class=\"jCAhz ChMk0b\"><span class=\"ryNqvb\">interop\u00e9rabilit\u00e9 pr\u00e9-silicium avec les c\u0153urs ARM.<\/span><\/span><\/span><\/p>\n<p><span class=\"HwtZe\" lang=\"fr\"><span class=\"jCAhz ChMk0b\"><span class=\"ryNqvb\">Le moniteur IP PVT de la famille Synopsys Silicon Lifecycle Management, d\u00e9velopp\u00e9 au Royaume-Uni, peut \u00e9galement \u00eatre int\u00e9gr\u00e9 dans les c\u0153urs ARM pour surveiller la sant\u00e9 des puces depuis le d\u00e9veloppement jusque sur le terrain afin de mesurer et d&rsquo;optimiser les performances.<\/span><\/span> <\/span><\/p>\n<p><span class=\"HwtZe\" lang=\"fr\"><span class=\"jCAhz ChMk0b\"><span class=\"ryNqvb\">Les kits de mise en \u0153uvre Synopsys Fusion QuickStart (QIK) sont r\u00e9gl\u00e9s pour extraire le maximum des derni\u00e8res technologies de process 5, 4 et 3 nm.<\/span><\/span> <span class=\"jCAhz ChMk0b\"><span class=\"ryNqvb\">Ceux-ci incluent des scripts d&rsquo;impl\u00e9mentation et des guides de r\u00e9f\u00e9rence qui permettent aux premiers utilisateurs des nouveaux c\u0153urs Armv9.2 d&rsquo;acc\u00e9l\u00e9rer le d\u00e9lai de mise sur le march\u00e9 et d&rsquo;atteindre leurs objectifs de performances par watt.<\/span><\/span> <span class=\"jCAhz ChMk0b\"><span class=\"ryNqvb\">Ces QIK sont disponibles d\u00e8s aujourd&rsquo;hui sur demande.<\/span><\/span><\/span><\/p>\n<p><a href=\"http:\/\/www.arm.com\">www.arm.com<\/a><\/p>\n<p>&nbsp;<\/p>\n","protected":false},"excerpt":{"rendered":"<p>ARM a lanc\u00e9 sa nouvelle plateforme \u00ab\u00a0Total Compute Solution\u00a0\u00bb (TCS) avec son c\u0153ur de processeur le plus rapide jamais cr\u00e9\u00e9, le X4 et un syst\u00e8me de gestion de c\u0153ur pour une fabrication sur le process 3 nm de TSMC et le process 18A d&rsquo;Intel. \u00a0Cela peut contribuer \u00e0 r\u00e9soudre la confusion apparue r\u00e9cemment sur l&rsquo;ambition [&hellip;]<\/p>\n","protected":false},"author":34,"featured_media":422946,"comment_status":"closed","ping_status":"closed","sticky":true,"template":"","format":"standard","meta":{"_acf_changed":false,"footnotes":""},"categories":[886],"tags":[2456,1644,3302,3619],"domains":[47],"ppma_author":[1153,1138],"class_list":["post-423023","post","type-post","status-publish","format-standard","has-post-thumbnail","hentry","category-news-fr","tag-arm-fr","tag-cpu-2","tag-ip-fr","tag-synopsis","domains-electronique-eci"],"acf":[],"yoast_head":"<title>ARM lance l&#039;IP de c\u0153ur de processeur Cortex-X4 ...<\/title>\n<meta name=\"description\" content=\"ARM&#039;s TCS23 on TSMC\u2019s N3E and Intel 18A for laptop chips may go some way to addressing the confusion over reports it is making its own chip\" \/>\n<meta name=\"robots\" content=\"index, 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