{"id":422917,"date":"2023-05-28T16:39:23","date_gmt":"2023-05-28T14:39:23","guid":{"rendered":"https:\/\/www.eenewseurope.com\/?p=422917"},"modified":"2023-05-29T23:13:44","modified_gmt":"2023-05-29T21:13:44","slug":"tsmc-va-mettre-1000-milliards-de-transistors-3nm-et-2nm-dans-un-seul-boitier","status":"publish","type":"post","link":"https:\/\/www.ecinews.fr\/fr\/tsmc-va-mettre-1000-milliards-de-transistors-3nm-et-2nm-dans-un-seul-boitier\/","title":{"rendered":"TSMC va int\u00e9grer 1000 milliards de transistors dans un seul bo\u00eetier"},"content":{"rendered":"<h4><span class=\"HwtZe\" lang=\"fr\"><span class=\"jCAhz ChMk0b\"><span class=\"ryNqvb\">TSMC d\u00e9veloppe un composant complexe avec mille milliards de transistors, intensifiant sa concurrence avec Intel en tant que leader de la technologie de processus.<\/span><\/span><\/span><\/h4>\n<p><span class=\"HwtZe\" lang=\"fr\"><span class=\"jCAhz ChMk0b\"><span class=\"ryNqvb\">Il utilise d\u00e9j\u00e0 des technologies de chiplets et de substrats pour fabriquer le GPU MI300 d&rsquo;AMD avec un empilement de puces 3D 5 nm sur un substrat de base de 6 nm avec huit puces DRAM.<\/span><\/span> <span class=\"jCAhz ChMk0b\"><span class=\"ryNqvb\">Mais les technologies sont utilis\u00e9es maintenant pour des puces 3 nm plus complexes et plus grandes sur un substrat.<\/span><\/span> <\/span><\/p>\n<p><span class=\"HwtZe\" lang=\"fr\"><span class=\"jCAhz ChMk0b\"><span class=\"ryNqvb\">\u00ab\u00a0Nous sommes proches de ce stade, nous en avons la capacit\u00e9 et je ne peux pas annoncer le produit et le client\u00a0\u00bb, a d\u00e9clar\u00e9 aujourd&rsquo;hui Kevin Zhang, vice-pr\u00e9sident senior du d\u00e9veloppement commercial lors du TSMC Technology Symposium \u00e0 Amsterdam.<\/span><\/span> <span class=\"jCAhz ChMk0b\"><span class=\"ryNqvb\">\u00ab\u00a0Mais nous avons l&#8217;empilement de plusieurs grandes puces et le processus CoWoS.\u00a0\u00bb<\/span><\/span> <span class=\"jCAhz ChMk0b\"><span class=\"ryNqvb\">Une partie du probl\u00e8me est le temps de cycle plus long de la technologie de traitement 3 nm et le process CoWoS ajout\u00e9 pour assembler tous les puces entre elles.<\/span><\/span><\/span><\/p>\n<p><span class=\"HwtZe\" lang=\"fr\"><span class=\"jCAhz ChMk0b\"><span class=\"ryNqvb\">\u00ab\u00a0La fabrication de puces 3 nm est d\u00e9j\u00e0 un long process et nous devons ensuite passer par le process d&#8217;empilement; avec une adoption plus large de la technologie, nous verrons ce temps de cycle diminuer.<\/span><\/span> <span class=\"jCAhz ChMk0b\"><span class=\"ryNqvb\">La technologie Chiplet en est encore \u00e0 ses balbutiements.<\/span><\/span><\/span><\/p>\n<ul>\n<li><a href=\"https:\/\/www.eenewseurope.com\/en\/intel-prepares-for-trillion-transistor-era-shake-up\/\">Intel prepares for trillion transistor era shake up<\/a><\/li>\n<li><a href=\"https:\/\/www.eenewseurope.com\/en\/power-limits-the-trillion-transistor-era-say-intel-tesla\/\">Power limits the trillion transistor era say Intel, Tesla<\/a><\/li>\n<\/ul>\n<p><span class=\"HwtZe\" lang=\"fr\"><span class=\"jCAhz ChMk0b\"><span class=\"ryNqvb\">Le passage au bo\u00eetier de mille milliards de transistors \u00e0\u00a0 est rendu possible par la prochaine g\u00e9n\u00e9ration du processus d&rsquo;interposition de TSMC, COWoS-L, qui sera disponible l&rsquo;ann\u00e9e prochaine.<\/span><\/span> <\/span><\/p>\n<p><span class=\"HwtZe\" lang=\"fr\"><span class=\"jCAhz ChMk0b\"><span class=\"ryNqvb\">\u00ab\u00a0Nous d\u00e9veloppons actuellement une technologie CoWoS-L de taille de r\u00e9ticule 6x avec la technologie d&rsquo;interposition Super Carrier\u00a0\u00bb, a d\u00e9clar\u00e9 Yujun Li, directeur du d\u00e9veloppement commercial de TSMC pour la division commerciale du calcul haute performance lors du symposium.<\/span><\/span> <span class=\"jCAhz ChMk0b\"><span class=\"ryNqvb\">Avec une taille de r\u00e9ticule de 858 mm2 (26 mm sur 33 mm), cela signifie que le syst\u00e8me dans le bo\u00eetier aura jusqu&rsquo;\u00e0 5 148 mm2.<\/span><\/span> <span class=\"jCAhz ChMk0b\"><span class=\"ryNqvb\">Cela permet plus de chiplets ainsi que jusqu&rsquo;\u00e0 12 piles de m\u00e9moire \u00e0 large bande passante HBM3.<\/span><\/span><\/span><\/p>\n<p><span class=\"HwtZe\" lang=\"fr\"><span class=\"jCAhz ChMk0b\"><span class=\"ryNqvb\">La soci\u00e9t\u00e9 pr\u00e9voit un process 2 nm en 2025, le premier avec l&rsquo;architecture de transistor \u00e0 nanofeuilles, bien que la production principale se fera sur N2P en 2026 avec une alimentation sur l&rsquo;arri\u00e8re de la puce.<\/span><\/span> <span class=\"jCAhz ChMk0b\"><span class=\"ryNqvb\">\u00abLa nanofeuille commence \u00e0 2 nm et il est raisonnable de pr\u00e9voir qu&rsquo;elle sera facilement utilis\u00e9e pendant au moins deux g\u00e9n\u00e9rations.<\/span><\/span> A titre d&rsquo;<span class=\"jCAhz ChMk0b\"><span class=\"ryNqvb\">exemple, nous avons utilis\u00e9 FinFet pendant cinq g\u00e9n\u00e9rations, c&rsquo;est plus de dix ans.<\/span><\/span> <\/span><\/p>\n<p><span class=\"HwtZe\" lang=\"fr\"><span class=\"jCAhz ChMk0b\"><span class=\"ryNqvb\">La soci\u00e9t\u00e9 pr\u00e9voit \u00e9galement d&rsquo;avoir un process 6 nm avec une m\u00e9moire RRAM r\u00e9sistive disponible l&rsquo;ann\u00e9e prochaine pour les microcontr\u00f4leurs.<\/span><\/span> <span class=\"jCAhz ChMk0b\"><span class=\"ryNqvb\">\u00ab\u00a0N6 RRAM est plus \u00e9loign\u00e9 que 2026\u00a0\u00bb, a-t-il d\u00e9clar\u00e9.<\/span><\/span> <span class=\"jCAhz ChMk0b\"><span class=\"ryNqvb\">\u00ab\u00a0Les MCU ne font que passer \u00e0 16 nm actuellement et il faut g\u00e9n\u00e9ralement plusieurs ann\u00e9es pour y passer depuis 28 nm, probablement 5 ans, puis ils passeront \u00e0 6 nm.\u00a0\u00bb<\/span><\/span> <span class=\"jCAhz ChMk0b\"><span class=\"ryNqvb\">Cependant, les MCU avec RRAM sont consid\u00e9r\u00e9s comme une capacit\u00e9 cl\u00e9 pour les architectures zonales dans l&rsquo;automobile.<\/span><\/span><\/span><\/p>\n<p><a href=\"http:\/\/www.tsmc.com\">www.tsmc.com<\/a><\/p>\n<p>&nbsp;<\/p>\n","protected":false},"excerpt":{"rendered":"<p>TSMC d\u00e9veloppe un composant complexe avec mille milliards de transistors, intensifiant sa concurrence avec Intel en tant que leader de la technologie de processus. Il utilise d\u00e9j\u00e0 des technologies de chiplets et de substrats pour fabriquer le GPU MI300 d&rsquo;AMD avec un empilement de puces 3D 5 nm sur un substrat de base de 6 [&hellip;]<\/p>\n","protected":false},"author":34,"featured_media":422537,"comment_status":"closed","ping_status":"closed","sticky":true,"template":"","format":"standard","meta":{"_acf_changed":false,"footnotes":""},"categories":[883],"tags":[3607,3301,2541],"domains":[47],"ppma_author":[1153,1138],"class_list":["post-422917","post","type-post","status-publish","format-standard","has-post-thumbnail","hentry","category-technologies","tag-6nm","tag-chiplets-fr","tag-tsmc","domains-electronique-eci"],"acf":[],"yoast_head":"<title>TSMC va int\u00e9grer 1000 milliards de transistors dans un seul bo...<\/title>\n<meta name=\"description\" content=\"TSMC is developing a complex device for a customer with a trillion transistors, ramping up its competition with Intel in process technology\" \/>\n<meta name=\"robots\" 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