{"id":421269,"date":"2023-05-09T11:23:42","date_gmt":"2023-05-09T09:23:42","guid":{"rendered":"https:\/\/www.eenewseurope.com\/?p=421269"},"modified":"2023-05-09T21:54:19","modified_gmt":"2023-05-09T19:54:19","slug":"le-francais-menta-codasip-rejoignent-le-projet-ia-neuromorphique-risc-v-3d","status":"publish","type":"post","link":"https:\/\/www.ecinews.fr\/fr\/le-francais-menta-codasip-rejoignent-le-projet-ia-neuromorphique-risc-v-3d\/","title":{"rendered":"Le fran\u00e7ais Menta et Codasip rejoignent le projet IA neuromorphique RISC-V 3D"},"content":{"rendered":"<h4><span class=\"HwtZe\" lang=\"fr\"><span class=\"jCAhz ChMk0b\"><span class=\"ryNqvb\">Le laboratoire de recherche de Codasip, un d\u00e9veloppeur europ\u00e9en de processeurs RISC-V et la soci\u00e9t\u00e9 fran\u00e7aise de FPGAs embarqu\u00e9s Menta ont rejoint un projet de construction d&rsquo;une puce d&rsquo;IA neuromorphique 3D.<\/span><\/span><\/span><\/h4>\n<p><span class=\"HwtZe\" lang=\"fr\"><span class=\"jCAhz ChMk0b\"><span class=\"ryNqvb\">Le projet NimbleAI, d&rsquo;un montant de 10 millions d&rsquo;euros, vise \u00e0 d\u00e9velopper une puce d&rsquo;IA int\u00e9gr\u00e9e 3D de d\u00e9tection et de traitement neuromorphique d&rsquo;ici 2025.<\/span><\/span><\/span><\/p>\n<p><span class=\"HwtZe\" lang=\"fr\"> <span class=\"jCAhz ChMk0b\"><span class=\"ryNqvb\">Codasip Labs, dirig\u00e9 par le fondateur de Codasip Karel Masa\u0159\u00edk, va d\u00e9velopper un noyau RISC-V \u00e0 l&rsquo;aide de son outil Codasip Studio avec des extensions d&rsquo;instructions personnalis\u00e9es pour le r\u00e9seau de neurones neuromorphique, ou \u00e0 impulsions, pilot\u00e9 par les \u00e9v\u00e9nements, ainsi que son langage de description d&rsquo;architecture CodAL.<\/span><\/span> <span class=\"jCAhz ChMk0b\"><span class=\"ryNqvb\">Si tout se passe comme pr\u00e9vu, cela se traduira par la cr\u00e9ation d&rsquo;une architecture neuromorphique int\u00e9grale pour ex\u00e9cuter efficacement des algorithmes de vision par ordinateur pr\u00e9cis et diversifi\u00e9s pour les terminaux, explique la soci\u00e9t\u00e9.<\/span><\/span><\/span><\/p>\n<p><span class=\"HwtZe\" lang=\"fr\"><span class=\"jCAhz ChMk0b\"><span class=\"ryNqvb\">Ceux-ci sont g\u00e9n\u00e9ralement limit\u00e9s en ressources et en espace disponible.<\/span><\/span> <span class=\"jCAhz ChMk0b\"><span class=\"ryNqvb\">Les cas d&rsquo;utilisation incluent les appareils d&rsquo;imagerie m\u00e9dicale portables et aliment\u00e9s par batterie, les moniteurs intelligents pour les v\u00e9hicules autonomes ou m\u00eame les lunettes de suivi oculaire portables.<\/span><\/span><\/span><\/p>\n<ul>\n<li><a href=\"https:\/\/www.eenewseurope.com\/en\/synsense-boosts-10m-round-for-3d-neuromorphic-processor\/\">SynSense boosts $10m round for 3D neuromorphic AI chip<\/a><\/li>\n<li><a href=\"https:\/\/www.eenewseurope.com\/en\/designing-a-neuromorphic-3d-integrated-chip-eenews-interview\/\">Designing a neuromorphic 3D integrated chip<\/a><\/li>\n<li><a href=\"https:\/\/www.eenewseurope.com\/en\/intellisense-to-use-neuromorphic-ai-for-next-generation-cognitive-radio-chip\/\">Intellisense to use neuromorphic AI for next generation<\/a><\/li>\n<\/ul>\n<p><span class=\"HwtZe\" lang=\"fr\"><span class=\"jCAhz ChMk0b\"><span class=\"ryNqvb\">Le c\u0153ur sera ensuite mapp\u00e9 sur un eFPGA de Menta qui pourra \u00eatre mis \u00e0 jour r\u00e9guli\u00e8rement avec de nouveaux algorithmes.<\/span><\/span> <span class=\"jCAhz ChMk0b\"><span class=\"ryNqvb\">\u00ab Notre technologie a \u00e9t\u00e9 con\u00e7ue pour \u00eatre facilement int\u00e9gr\u00e9e aux technologies d&rsquo;autres partenaires qui, ensemble, sont essentielles pour l&rsquo;inf\u00e9rence d&rsquo;IA \u00e0 faible consommation et en constante \u00e9volution \u00bb, a d\u00e9clar\u00e9 Vincent Markus, PDG de Menta.<\/span><\/span> <span class=\"jCAhz ChMk0b\"><span class=\"ryNqvb\">Les algorithmes tels que ceux utilis\u00e9s par l&rsquo;IA \u00e9voluent 4 fois plus vite que la cadence de production d&rsquo;une puce donc la possibilit\u00e9 de reprogrammer le mat\u00e9riel des puces leur permet de s&rsquo;adapter en permanence \u00e0 ces besoins.<\/span><\/span> <span class=\"jCAhz ChMk0b\"><span class=\"ryNqvb\">Menta est actuellement la seule solution europ\u00e9enne industrialis\u00e9e pour la logique programmable embarqu\u00e9e et est impliqu\u00e9e dans plusieurs projets europ\u00e9ens tels que le projet EPI-SGA2, le projet PROMISE et le nouveau projet MOSAICs-LP.<\/span><\/span><\/span><\/p>\n<p><span class=\"HwtZe\" lang=\"fr\"><span class=\"jCAhz ChMk0b\"><span class=\"ryNqvb\">Parmi les autres 19 membres du projet il y a le fabricant de puces fran\u00e7ais GrAI Matter Labs et le fournisseur d&rsquo;outils EDA MZ Technologies ainsi que le CEA en France, l&rsquo;imec en Belgique, les universit\u00e9s de Manchester et Queen Mary au Royaume-Uni et TU Eindhoven aux Pays-Bas.<\/span><\/span> <\/span><\/p>\n<p><span class=\"HwtZe\" lang=\"fr\"><span class=\"jCAhz ChMk0b\"><span class=\"ryNqvb\">Le projet pr\u00e9voit d&rsquo;obtenir une am\u00e9lioration de l&rsquo;efficacit\u00e9 \u00e9nerg\u00e9tique de 100 fois et une r\u00e9duction de la latence de 50 fois gr\u00e2ce au calcul m\u00e9moire et \u00e0 l&rsquo;eFPGA, ainsi qu&rsquo;au stockage int\u00e9gr\u00e9 bas\u00e9 sur ReRAM avec des couches de circuit 3D utilisant des vias dans le silicium.<\/span><\/span><\/span><\/p>\n<p>&nbsp;<\/p>\n<blockquote class=\"wp-embedded-content\" data-secret=\"YX9t7RpJOX\"><p><a href=\"https:\/\/www.eenewseurope.com\/en\/space-and-time-vision-with-nimbleais-3d-chip-design\/\">Space and Time Vision with NimbleAI&#8217;s 3D Chip Design<\/a><\/p><\/blockquote>\n<p><iframe class=\"wp-embedded-content lazyload\" sandbox=\"allow-scripts\" security=\"restricted\" style=\"position: absolute; visibility: hidden;\" title=\"&#8220;Space and Time Vision with NimbleAI&#8217;s 3D Chip Design&#8221; &#8212; eeNews Europe\" data-src=\"https:\/\/www.eenewseurope.com\/en\/space-and-time-vision-with-nimbleais-3d-chip-design\/embed\/#?secret=Vm8wF2rU9x#?secret=YX9t7RpJOX\" data-secret=\"YX9t7RpJOX\" width=\"500\" height=\"282\" frameborder=\"0\" marginwidth=\"0\" marginheight=\"0\" scrolling=\"no\" src=\"data:image\/svg+xml;base64,PHN2ZyB3aWR0aD0iMSIgaGVpZ2h0PSIxIiB4bWxucz0iaHR0cDovL3d3dy53My5vcmcvMjAwMC9zdmciPjwvc3ZnPg==\" data-load-mode=\"1\"><\/iframe><\/p>\n<p><a href=\"http:\/\/www.nimbleai.eu\">www.nimbleai.eu<\/a>; <a href=\"http:\/\/www.codasip.com\">www.codasip.com<\/a>; <a href=\"http:\/\/www.menta-efpga.com\">www.menta-efpga.com<\/a><\/p>\n<p>&nbsp;<\/p>\n<p>&nbsp;<\/p>\n","protected":false},"excerpt":{"rendered":"<p>Le laboratoire de recherche de Codasip, un d\u00e9veloppeur europ\u00e9en de processeurs RISC-V et la soci\u00e9t\u00e9 fran\u00e7aise de FPGAs embarqu\u00e9s Menta ont rejoint un projet de construction d&rsquo;une puce d&rsquo;IA neuromorphique 3D. Le projet NimbleAI, d&rsquo;un montant de 10 millions d&rsquo;euros, vise \u00e0 d\u00e9velopper une puce d&rsquo;IA int\u00e9gr\u00e9e 3D de d\u00e9tection et de traitement neuromorphique d&rsquo;ici [&hellip;]<\/p>\n","protected":false},"author":6,"featured_media":420725,"comment_status":"closed","ping_status":"closed","sticky":true,"template":"","format":"standard","meta":{"_acf_changed":false,"footnotes":""},"categories":[886],"tags":[2776,1674,3641],"domains":[47],"ppma_author":[1138],"class_list":["post-421269","post","type-post","status-publish","format-standard","has-post-thumbnail","hentry","category-news-fr","tag-ia-neuromorphique","tag-risc-v-2","tag-risc-v-fr","domains-electronique-eci"],"acf":[],"yoast_head":"<title>Le fran\u00e7ais Menta et Codasip rejoignent le projet IA neuromorp...<\/title>\n<meta name=\"description\" content=\"Codasip Labs et la soci\u00e9t\u00e9 de FPGA embarqu\u00e9s Menta ont rejoint un projet visant \u00e0 construire une puce d&#039;IA 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