{"id":419360,"date":"2023-04-18T11:49:21","date_gmt":"2023-04-18T09:49:21","guid":{"rendered":"https:\/\/www.eenewseurope.com\/?p=419360"},"modified":"2023-04-18T12:01:51","modified_gmt":"2023-04-18T10:01:51","slug":"semidynamics-coeurs-risc-v-ip-entierement-personnalisables-et-independants-du-processus","status":"publish","type":"post","link":"https:\/\/www.ecinews.fr\/fr\/semidynamics-coeurs-risc-v-ip-entierement-personnalisables-et-independants-du-processus\/","title":{"rendered":"Semidynamics : c\u0153urs RISC-V IP enti\u00e8rement personnalisables et ind\u00e9pendants du processus"},"content":{"rendered":"<h3><span style=\"font-size: 16px;\">Cr\u00e9e en 2016 \u00e0 Barcelone, le concepteur espagnol de semiconducteurs sans fabrication\u00a0 <strong>Semidynamics<\/strong> a annonc\u00e9 la premi\u00e8re famille de c\u0153urs RISC-V 64 bits enti\u00e8rement personnalisable, id\u00e9ale pour traiter les\u00a0 traiter les grandes quantit\u00e9s de donn\u00e9s des applications ce l&rsquo;IA, de l&rsquo;apprentissage automatique (ML) et du calcul \u00e0 haute performance (HPC). Ces c\u0153urs ne d\u00e9pendent d&rsquo;aucun processus et des versions jusqu&rsquo;\u00e0 5 nm sont d\u00e9j\u00e0 disponibles.<\/span><\/h3>\n<p><img decoding=\"async\" class=\"wp-image-419377 alignleft lazyload\" data-src=\"https:\/\/www.eenewseurope.com\/wp-content\/uploads\/2023\/04\/Semidynamics-Roger-Espasa-234x300.jpg\" alt=\"\" width=\"102\" height=\"131\" data-srcset=\"https:\/\/www.ecinews.fr\/wp-content\/uploads\/2023\/04\/Semidynamics-Roger-Espasa-234x300.jpg 234w, https:\/\/www.ecinews.fr\/wp-content\/uploads\/2023\/04\/Semidynamics-Roger-Espasa-799x1024.jpg 799w, https:\/\/www.ecinews.fr\/wp-content\/uploads\/2023\/04\/Semidynamics-Roger-Espasa-768x984.jpg 768w, https:\/\/www.ecinews.fr\/wp-content\/uploads\/2023\/04\/Semidynamics-Roger-Espasa-scaled.jpg 843w\" data-sizes=\"(max-width: 102px) 100vw, 102px\" src=\"data:image\/svg+xml;base64,PHN2ZyB3aWR0aD0iMSIgaGVpZ2h0PSIxIiB4bWxucz0iaHR0cDovL3d3dy53My5vcmcvMjAwMC9zdmciPjwvc3ZnPg==\" style=\"--smush-placeholder-width: 102px; --smush-placeholder-aspect-ratio: 102\/131;\" \/>Roger Espasa, PDG et fondateur de Semidynamics, explique : \u00ab\u00a0Jusqu&rsquo;\u00e0 pr\u00e9sent, les c\u0153urs de processeurs RISC-V avaient des configurations d\u00e9finies par le fournisseur ou un nombre limit\u00e9 d&rsquo;options configurables telles que la capacit\u00e9 du cache, la configuration du bus d&rsquo;adresse, les interfaces et quelques autres param\u00e8tres de contr\u00f4le. Nos nouveaux c\u0153urs IP permettent au concepteur de contr\u00f4ler totalement la configuration, qu&rsquo;il s&rsquo;agisse de nouvelles instructions, d&rsquo;espaces d&rsquo;adressage s\u00e9par\u00e9s, de nouvelles fonctionnalit\u00e9s d&rsquo;acc\u00e8s \u00e0 la m\u00e9moire, etc. Cela signifie que nous pouvons adapter pr\u00e9cis\u00e9ment un module aux besoins de chaque projet, de sorte qu&rsquo;il n&rsquo;y a pas de\u00a0 surco\u00fbts ou de compromis inutiles. Plus important encore, nous pouvons mettre en \u0153uvre les caract\u00e9ristiques de la \u00ab\u00a0sp\u00e9cificit\u00e9e propri\u00e9taire\u00a0\u00bb d&rsquo;un client dans la RTL en quelques semaines, ce que personne d&rsquo;autre ne propose. Tous les concepteurs qui utilisent RISC-V veulent disposer de l&rsquo;ensemble optimal puissance, performance et taille, ainsi que de caract\u00e9ristiques personnelles uniques, ce que nous sommes en mesure d&rsquo;offrir.\u00a0\u00bb<\/p>\n<p><strong>Le coeur Altrevido<\/strong><\/p>\n<p>Le premier membre de\u00a0 la famille, dont les licences sont aujourd&rsquo;hui\u00a0 disponibles, est le c\u0153ur Atrevido\u2122. Il est dot\u00e9 d&rsquo;un m\u00e9canisme d&rsquo;ordonnancement hors norme combin\u00e9 \u00e0 la technologie propri\u00e9taire Gazzillion\u2122 de l&rsquo;entreprise, de sorte qu&rsquo;il peut traiter des donn\u00e9es tr\u00e8s \u00e9parses \u00e0 longues latences et avec des syst\u00e8mes de m\u00e9moire \u00e0 large bande passante qui sont typiques des applications actuelles d&rsquo;apprentissage automatique. La technologie Gazzillion \u00e9limine les probl\u00e8mes de latence qui pourraient appara\u00eetre lors de l&rsquo;utilisation de la technologie CXL pour que l&rsquo;on puisse acc\u00e9der \u00e0 la m\u00e9moire distante. Cette technologie est sp\u00e9cialement con\u00e7ue pour les syst\u00e8mes de r\u00e9f\u00e9rence qui constituent un \u00e9l\u00e9ment cl\u00e9 de l&rsquo;apprentissage automatique dans les centres de donn\u00e9es. En prenant en charge plus d&rsquo;une centaine de rat\u00e9s par c\u0153ur, il est possible de concevoir un SoC qui fournit des donn\u00e9es tr\u00e8s \u00e9parses aux moteurs de calcul sans investissement important en silicium. En outre, le c\u0153ur peut \u00eatre configur\u00e9 de 2 \u00e0 4 voies pour aider \u00e0 acc\u00e9l\u00e9rer les \u00e9l\u00e9ments moins parall\u00e8les des syst\u00e8mes de reconnaissance. Pour les charges de travail les plus exigeantes, telles que le HPC, le c\u0153ur Atrevido prend en charge de grandes capacit\u00e9s de m\u00e9moire avec son canal de donn\u00e9es natif de 64 bits et ses canaux d&rsquo;adresses physiques de 48 bits.<\/p>\n<p>Gr\u00e2ce \u00e0 sa prise en charge compl\u00e8te des MMU, Atrevido est \u00e9galement pr\u00eat pour Linux et prend en charge les environnements multiprocesseurs \u00e0 coh\u00e9rence de cache \u00e0 partir de deux c\u0153urs et jusqu&rsquo;\u00e0 des centaines de c\u0153urs. Il est pr\u00eat pour les vecteurs, supportant \u00e0 la fois la sp\u00e9cification vectorielle RISC-V 1.0 et la future interface vectorielle ouverte Semidynamics.<\/p>\n<p>En conclusion de Roger Espasa, : \u00ab\u00a0Nous avons \u00e9t\u00e9 en mode furtif pendant notre cr\u00e9ation de l&rsquo;architecture de base que la communaut\u00e9 RISC-V que nou souhaitions &#8211; une architecture enti\u00e8rement personnalisable, et pas seulement sur quelques param\u00e8tres \u00e0 ajuster. Notre noyau RISC-V est sans doute le plus complexe pouvant \u00eatre totalement configur\u00e9 pour r\u00e9pondre avec pr\u00e9cision aux besoins sp\u00e9cifiques de chaque projet, plut\u00f4t que d&rsquo;avoir \u00e0 utiliser un noyau pr\u00eat \u00e0 l&#8217;emploi et \u00e0 faire des compromis.<\/p>\n<p><a href=\"Semidynamics%20- The world\u2019s only fully configurable 64-bit RISC-V processor IP\">Semidynamics<\/a><\/p>\n<p>&nbsp;<\/p>\n<p>&nbsp;<\/p>\n<p>&nbsp;<\/p>\n","protected":false},"excerpt":{"rendered":"<p>Cr\u00e9e en 2016 \u00e0 Barcelone, le concepteur espagnol de semiconducteurs sans fabrication\u00a0 Semidynamics a annonc\u00e9 la premi\u00e8re famille de c\u0153urs RISC-V 64 bits enti\u00e8rement personnalisable, id\u00e9ale pour traiter les\u00a0 traiter les grandes quantit\u00e9s de donn\u00e9s des applications ce l&rsquo;IA, de l&rsquo;apprentissage automatique (ML) et du calcul \u00e0 haute performance (HPC). Ces c\u0153urs ne d\u00e9pendent d&rsquo;aucun [&hellip;]<\/p>\n","protected":false},"author":11,"featured_media":419375,"comment_status":"closed","ping_status":"closed","sticky":true,"template":"","format":"standard","meta":{"_acf_changed":false,"footnotes":""},"categories":[881],"tags":[3297,1933,3641,1674,2643],"domains":[47],"ppma_author":[1143],"class_list":["post-419360","post","type-post","status-publish","format-standard","has-post-thumbnail","hentry","category-nouveaux-produits","tag-intelligence-artificielle-ia","tag-processeur-risc-v","tag-risc-v-fr","tag-risc-v-2","tag-soc-fr","domains-electronique-eci"],"acf":[],"yoast_head":"<title>Semidynamics : c\u0153urs RISC-V IP enti\u00e8rement personnalisables e...<\/title>\n<meta name=\"description\" content=\"c\u0153urs RISC-V 64 bits enti\u00e8rement personnalisable, traitement des % % donn\u00e9s des applications ce l&#039;IA, de l&#039;apprentissage automatique (ML) et du calcul \u00e0...\" \/>\n<meta name=\"robots\" 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