{"id":417280,"date":"2023-03-23T17:17:38","date_gmt":"2023-03-23T16:17:38","guid":{"rendered":"https:\/\/www.eenewseurope.com\/?p=417280"},"modified":"2023-03-27T16:42:14","modified_gmt":"2023-03-27T14:42:14","slug":"risc-v-booste-avec-le-nouveau-compilateur-llvm-16-open-source","status":"publish","type":"post","link":"https:\/\/www.ecinews.fr\/fr\/risc-v-booste-avec-le-nouveau-compilateur-llvm-16-open-source\/","title":{"rendered":"RISC-V boost\u00e9 avec le nouveau compilateur LLVM 16 open source"},"content":{"rendered":"

Le d\u00e9veloppement de puces RISC-V est acc\u00e9l\u00e9r\u00e9 de fa\u00e7on significative avec la derni\u00e8re version du compilateur open source LLVM qui sous-tend de nombreux outils de l’industrie.<\/span><\/span> <\/span><\/h2>\n

Pour la premi\u00e8re fois, l’architecture dispose d’un guide de l’utilisateur pour la cible RISC-V afin de documenter l’\u00e9tat du support au sein de LLVM pour diverses extensions du jeu d’instructions RISC-V.<\/span><\/span> LLVM prend actuellement enti\u00e8rement en charge RV32I et RV64I.<\/span><\/span> RV32E est pris en charge par les outils bas\u00e9s sur l’assembleur uniquement, tandis que RV128I n’est pas pris en charge.<\/span><\/span> <\/span><\/p>\n

Dans le m\u00eame temps, le support des extensions non ratifi\u00e9es Zbe, Zbf, Zbm, Zbp, Zbr et Zbt a \u00e9t\u00e9 supprim\u00e9e, tandis que le support a \u00e9t\u00e9 ajout\u00e9 pour les extensions exp\u00e9rimentales Zca, Zcd, Zcf, Zihintntl, Ztso et Zawrs.<\/span><\/span> Il s’agit \u00e9galement de la premi\u00e8re version o\u00f9 la vectorisation \u00e9volutive a \u00e9t\u00e9 activ\u00e9e par d\u00e9faut, ce qui facilite le d\u00e9veloppement de syst\u00e8mes plus performants.<\/span><\/span><\/span><\/p>\n

LLVM met \u00e0 jour sa technologie de compilateur tous les six mois pour r\u00e9pondre aux exigences des d\u00e9veloppeurs.<\/span><\/span> <\/span><\/h3>\n

L’un des principaux probl\u00e8mes de RISC-V est l’utilisation d’extensions personnalis\u00e9es qui peuvent conduire \u00e0 la fragmentation de l’\u00e9cosyst\u00e8me.<\/span><\/span> Les extensions de fournisseur sont des extensions qui ne sont pas normalis\u00e9es par RISC-V International, et sont plut\u00f4t d\u00e9finies par un fournisseur de mat\u00e9riel et correspondent \u00e0 peu pr\u00e8s \u00e0 la d\u00e9finition d’une extension non standard de la section 1.3 du Volume I: sp\u00e9cification RISC-V Unprivileged ISA.<\/span><\/span> LLVM a l’intention d’accepter \u00e0 terme \u00e0 la fois les extensions personnalis\u00e9es et les extensions non conformes et l’inclusion d’une extension de fournisseur sera consid\u00e9r\u00e9e au cas par cas.<\/span><\/span><\/span><\/p>\n

L’optimisation de la branche avant courte b\u00e9n\u00e9fique pour le SiFive Series 7 a \u00e9t\u00e9 impl\u00e9ment\u00e9e et un mod\u00e8le de processeur Syntacore SCR1 a \u00e9t\u00e9 ajout\u00e9.<\/span><\/span><\/span><\/p>\n

Le projet LLVM<\/h3>\n

disponible \u00e0 https:\/\/github.com\/llvm\/llvm-project<\/a><\/p>\n

Le projet LLVM comporte de nombreux composants.<\/span><\/span> Le c\u0153ur du projet s’appelle lui-m\u00eame \u00ab LLVM \u00bb.<\/span><\/span> Celui-ci contient tous les outils, biblioth\u00e8ques et fichiers d’en-t\u00eate n\u00e9cessaires pour traiter les repr\u00e9sentations interm\u00e9diaires et les convertir en fichiers objets.<\/span><\/span> Les outils incluent un assembleur, un d\u00e9sassembleur, un analyseur de bitcode et un optimiseur de bitcode.<\/span><\/span> Les langages de type C utilisent l’interface Clang<\/a>.<\/span><\/span> Ce composant compile le code C, C++, Objective-C et Objective-C++ en bitcode LLVM – et \u00e0 partir de l\u00e0 en fichiers objets, \u00e0 l’aide de LLVM.<\/span><\/span> <\/span><\/p>\n

Les autres composants incluent : la biblioth\u00e8que standard libc++ C++ libc++ C++ standard library<\/a>, l’\u00e9diteur de liens LLD LLD linker<\/a>, et autres.<\/span><\/span><\/span><\/p>\n

Liens utiles<\/h3>\n

Suivre ECInews sur Google news<\/a><\/p>\n

discourse.llvm.org\/t\/llvm-16-0-0-release\/69326<\/a><\/p>\n

User Guide for RISC-V Target<\/a><\/p>\n

\u00a0<\/p>\n","protected":false},"excerpt":{"rendered":"

Le d\u00e9veloppement de puces RISC-V est acc\u00e9l\u00e9r\u00e9 de fa\u00e7on significative avec la derni\u00e8re version du compilateur open source LLVM qui sous-tend de nombreux outils de l’industrie.<\/p>\n","protected":false},"author":34,"featured_media":417227,"comment_status":"closed","ping_status":"closed","sticky":true,"template":"","format":"standard","meta":{"_acf_changed":false,"footnotes":""},"categories":[886],"tags":[3113,3641,1674],"domains":[47],"ppma_author":[1153,1138],"class_list":["post-417280","post","type-post","status-publish","format-standard","has-post-thumbnail","hentry","category-news-fr","tag-compilateurs","tag-risc-v-fr","tag-risc-v-2","domains-electronique-eci"],"acf":[],"yoast_head":"RISC-V boost\u00e9 avec le nouveau compilateur LLVM 16 open source ...<\/title>\n<meta name=\"description\" content=\"Le d\u00e9veloppement de puces RISC-V est acc\u00e9l\u00e9r\u00e9 de fa\u00e7on significative avec la derni\u00e8re version du compilateur open source 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