{"id":409493,"date":"2022-12-30T17:25:28","date_gmt":"2022-12-30T16:25:28","guid":{"rendered":"https:\/\/www.eenewseurope.com\/?p=409493"},"modified":"2023-01-02T10:25:39","modified_gmt":"2023-01-02T09:25:39","slug":"e270m-de-lue-pour-des-chiplets-risc-v-permettant-des-supercalculateurs-exascale","status":"publish","type":"post","link":"https:\/\/www.ecinews.fr\/fr\/e270m-de-lue-pour-des-chiplets-risc-v-permettant-des-supercalculateurs-exascale\/","title":{"rendered":"Chiplets RISC-V pour supercalculateurs exascale : l&rsquo;UE promet 270 m\u20ac"},"content":{"rendered":"<h2><span class=\"HwtZe\" lang=\"fr\"><span class=\"jCAhz ChMk0b\"><span class=\"ryNqvb\">EuroHPC doit lancer un appel \u00e0 projet en janvier 2023 pour des projets de puces RISC-V avec un soutien de 270 millions d&rsquo;euros.<\/span><\/span><\/span><\/h2>\n<p><span class=\"HwtZe\" lang=\"fr\"><span class=\"jCAhz ChMk0b\"><span class=\"ryNqvb\">Un accord-cadre de partenariat (FPA) vise \u00e0 mettre en place un partenariat \u00e0 long terme entre la \u00ab\u00a0joint undertaking EuroHPC\u00a0\u00bb et un consortium d&rsquo;industriels, d&rsquo;organismes de recherche et d&rsquo;institutions sp\u00e9cialis\u00e9s dans le calcul haute performance.<\/span><\/span> <span class=\"jCAhz ChMk0b\"><span class=\"ryNqvb\">Cela conduira \u00e0 une \u00ab\u00a0initiative de R&amp;D strat\u00e9gique et ambitieuse contribuant au d\u00e9veloppement de technologies mat\u00e9rielles et logicielles HPC innovantes bas\u00e9es sur l&rsquo;\u00e9cosyst\u00e8me ouvert RISC-V\u00a0\u00bb.<\/span><\/span> <\/span><\/p>\n<p><span class=\"HwtZe\" lang=\"fr\"><span class=\"jCAhz ChMk0b\"><span class=\"ryNqvb\">Cette initiative sera suivie d&rsquo;un plan de construction et de d\u00e9ploiement de supercalculateurs exascale et post-exascale bas\u00e9s sur la technologie d\u00e9velopp\u00e9e en commun.<\/span><\/span><\/span><\/p>\n<p>&nbsp;<\/p>\n<ul>\n<li>\n<p class=\"title\"><a title=\"Axelera lance une plateforme IA RISC-V pour la vision Edge\" href=\"https:\/\/www.ecinews.fr\/fr\/axelera-lance-une-plateforme-ia-risc-v-pour-la-vision-edge\/\" target=\"_blank\" rel=\"noopener\">Axelera lance une plateforme IA RISC-V pour la vision Edge<\/a><\/p>\n<\/li>\n<li>\n<p class=\"title\"><a title=\"Microcontr\u00f4leur RISC-V 32-bits automobile made in France\" href=\"https:\/\/www.ecinews.fr\/fr\/microcontroleur-risc-v-32-bits-automobile-made-in-france\/\" target=\"_blank\" rel=\"noopener\">Microcontr\u00f4leur RISC-V 32-bits automobile made in France<\/a><\/p>\n<\/li>\n<li><a href=\"https:\/\/www.eenewseurope.com\/en\/e8m-project-for-europes-first-risc-v-supercomputer-chip\/\">\u20ac8m project for Europe&rsquo;s first RISC-V supercomputer chip<\/a><\/li>\n<li><a href=\"https:\/\/www.eenewseurope.com\/en\/european-supercomputer-project-receives-risc-v-test-chips\/\">European supercomputer project receives RISC-V test chips<\/a><\/li>\n<\/ul>\n<p><span class=\"HwtZe\" lang=\"fr\"><span class=\"jCAhz ChMk0b\"><span class=\"ryNqvb\">Pour \u00e9viter la fragmentation des programmes pr\u00e9c\u00e9dents, ce partenariat sera mis en place \u00e0 travers un FPA unique avec plusieurs conventions de subvention sp\u00e9cifiques parall\u00e8les et cons\u00e9cutives compl\u00e9mentaires (Specific Grant Agreements (SGAs) ) qui r\u00e9aliseront les diff\u00e9rentes activit\u00e9s dans un cadre commun.<\/span><\/span> <span class=\"jCAhz ChMk0b\"><span class=\"ryNqvb\">Les candidatures ouvriront le 26 janvier 2023 et se cl\u00f4tureront le 4 avril.<\/span><\/span> <\/span><\/p>\n<p><span class=\"HwtZe\" lang=\"fr\"><span class=\"jCAhz ChMk0b\"><span class=\"ryNqvb\">Le programme couvrira la conception, le d\u00e9veloppement, les tests, le tape-out de diff\u00e9rentes g\u00e9n\u00e9rations de processeurs et\/ou d&rsquo;acc\u00e9l\u00e9rateurs RISC-V haut de gamme \u00e9conomes en \u00e9nergie, en particulier les approches bas\u00e9es sur les puces, ainsi que l&rsquo;int\u00e9gration dans des bancs d&rsquo;essai et au moins<\/span><\/span> <span class=\"jCAhz ChMk0b\"><span class=\"ryNqvb\">un pilote dans des environnements pr\u00e9-op\u00e9rationnels dans des centres de calcul intensif pour les tests utilisateurs et la validation.<\/span><\/span><\/span><\/p>\n<ul>\n<li>\n<p class=\"title\"><a title=\"Le processeur s\u00e9curis\u00e9 TESIC Secure made in France utilise RISC-V\" href=\"https:\/\/www.ecinews.fr\/fr\/le-processeur-securise-tesic-secure-made-in-france-utilise-risc-v\/\" target=\"_blank\" rel=\"noopener\">Le processeur s\u00e9curis\u00e9 TESIC Secure made in France utilise RISC-V<\/a><\/p>\n<\/li>\n<li>\n<p class=\"title\"><a title=\"Android Open Source Project port\u00e9 sur RISC-V\" href=\"https:\/\/www.ecinews.fr\/fr\/android-open-source-project-porte-sur-risc-v\/\" target=\"_blank\" rel=\"noopener\">Android Open Source Project port\u00e9 sur RISC-V<\/a><\/p>\n<\/li>\n<li><a href=\"https:\/\/www.eenewseurope.com\/en\/e16m-project-to-secure-the-chiplet-supply-chain-in-europe\/\">\u20ac16m project to secure the chiplet supply chain in Europe<\/a><\/li>\n<\/ul>\n<p><span class=\"HwtZe\" lang=\"fr\"><span class=\"jCAhz ChMk0b\"><span class=\"ryNqvb\">Il vise \u00e9galement \u00e0 d\u00e9velopper la pile logicielle compl\u00e8te et l&rsquo;\u00e9cosyst\u00e8me logiciel associ\u00e9 pour les processeurs et\/ou acc\u00e9l\u00e9rateurs, en adressant les couches syst\u00e8me, middleware et applicatives.<\/span><\/span> <span class=\"jCAhz ChMk0b\"><span class=\"ryNqvb\">Il explorera et exploitera \u00e9galement les capacit\u00e9s de fabrication existantes en Europe, y compris les lignes pilotes existantes ou en cours de d\u00e9veloppement, pour fabriquer les composants requis, ce qui sera possible avec une approche chiplet mais n\u00e9cessitera un traitement de pointe tel que le process Intel 4 en cours d&rsquo;installation en Irlande.<\/span><\/span><\/span><\/p>\n<ul>\n<li><a href=\"https:\/\/www.eenewseurope.com\/en\/1400-risc-v-cores-for-on-chip-machine-learning\/\">1400 RISC-V cores for on-chip machine learning<\/a><\/li>\n<li>\n<p class=\"title\"><a title=\"Circuit de test pour supercalculateurs europ\u00e9en EPI EPAC1.0 RISC-V\" href=\"https:\/\/www.ecinews.fr\/fr\/circuit-de-test-pour-supercalculateurs-europeen-epi-epac1-0-risc-v\/\" target=\"_blank\" rel=\"noopener\">Circuit de test pour supercalculateurs europ\u00e9en EPI EPAC1.0 RISC-V<\/a><\/p>\n<\/li>\n<\/ul>\n<p><span class=\"HwtZe\" lang=\"fr\"><span class=\"jCAhz ChMk0b\"><span class=\"ryNqvb\">Le projet EPI a d\u00e9j\u00e0 r\u00e9alis\u00e9 le tape out de puces de test RISC-V en utilisant un process de 22 nm chez GlobalFounrdies \u00e0 Dresde.<\/span><\/span> <span class=\"jCAhz ChMk0b\"><span class=\"ryNqvb\">Cela a r\u00e9uni 28 partenaires de 10 pays europ\u00e9ens, avec un objectif similaire de rendre l&rsquo;UE ind\u00e9pendante dans les technologies de puces HPC et l&rsquo;infrastructure HPC.<\/span><\/span> <\/span><\/p>\n<p><span class=\"HwtZe\" lang=\"fr\"><span class=\"jCAhz ChMk0b\"><span class=\"ryNqvb\">Le FPA veillera \u00e9galement \u00e0 ce que toute la propri\u00e9t\u00e9 intellectuelle g\u00e9n\u00e9r\u00e9e dans le cadre de l&rsquo;initiative reste dans l&rsquo;UE et ne soit pas transf\u00e9r\u00e9e vers des pays tiers, en consacrant un effort appropri\u00e9 \u00e0 la gestion, \u00e0 la protection et \u00e0 l&rsquo;exploitation de la propri\u00e9t\u00e9 intellectuelle, telles que les licences et les garanties de propri\u00e9t\u00e9 intellectuelle.<\/span><\/span><\/span><\/p>\n<p>&nbsp;<\/p>\n<p><a href=\"https:\/\/digital-strategy.ec.europa.eu\/en\/library\/recommendations-and-roadmap-european-sovereignty-open-source-hardware-software-and-risc-v\">Recommendations and Roadmap for European Sovereignty in Open Source Hardware, Software, and RISC-V Technologies<\/a><\/p>\n<p><a href=\"https:\/\/eurohpc-ju.europa.eu\/framework-partnership-agreement-fpa-developing-large-scale-european-initiative-high-performance_en\">eurohpc-ju.europa.eu<\/a><\/p>\n","protected":false},"excerpt":{"rendered":"<p>\u20ac270m de l&rsquo;UE pour des chiplets RISC-V permettant des supercalculateurs exascale<\/p>\n","protected":false},"author":34,"featured_media":266519,"comment_status":"closed","ping_status":"closed","sticky":false,"template":"","format":"standard","meta":{"_acf_changed":false,"footnotes":""},"categories":[883],"tags":[1645,906,1674,3641],"domains":[47],"ppma_author":[1153,1138],"class_list":["post-409493","post","type-post","status-publish","format-standard","has-post-thumbnail","hentry","category-technologies","tag-hpc-2","tag-mpus-mcus-fr","tag-risc-v-2","tag-risc-v-fr","domains-electronique-eci"],"acf":[],"yoast_head":"<title>Chiplets RISC-V pour supercalculateurs exascale : l&#039;UE promet 2...<\/title>\n<meta name=\"description\" content=\"EuroHPC doit lancer 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