{"id":4031,"date":"2021-09-13T16:03:51","date_gmt":"2021-09-13T16:03:51","guid":{"rendered":"https:\/\/\/microchip-devoile-le-phy-ethernet-1-6t-le-plus-compact-du-marche\/"},"modified":"2021-09-13T16:03:51","modified_gmt":"2021-09-13T16:03:51","slug":"microchip-devoile-le-phy-ethernet-1-6t-le-plus-compact-du-marche","status":"publish","type":"post","link":"https:\/\/www.ecinews.fr\/fr\/microchip-devoile-le-phy-ethernet-1-6t-le-plus-compact-du-marche\/","title":{"rendered":"Microchip d\u00e9voile le PHY Ethernet 1.6T le plus compact du march\u00e9"},"content":{"rendered":"<p>Pour fournir une bande passante plus \u00e9lev\u00e9e, ces conceptions doivent surmonter les probl\u00e8mes d&rsquo;int\u00e9grit\u00e9 du signal associ\u00e9s \u00e0 la migration g\u00e9n\u00e9rale vers la connectivit\u00e9 SerDes (S\u00e9rialiseur\/D\u00e9-s\u00e9rialiseur) PAM4 112&nbsp;Gbits\/s, n\u00e9cessaire pour prendre en charge les fibres optiques enfichables, les fonds de panier syst\u00e8mes et les processeurs de paquets les plus r\u00e9cents. Ces d\u00e9fis peuvent d\u00e9sormais \u00eatre relev\u00e9s gr\u00e2ce \u00e0 la solution PHY (couche physique) 1,6&nbsp;Tbits\/s et faible consommation la plus compacte du march\u00e9, propos\u00e9e par Microchip Technology Inc. avec son <a href=\"http:\/\/www.microchip.com\/META-DX2L\">META-DX2L PM6200<\/a> qui r\u00e9duit la consommation par port de 35% par rapport \u00e0 son pr\u00e9d\u00e9cesseur PAM4 56&nbsp;Gbits\/s, le META-DX1, premi\u00e8re solution PHY de niveau T\u00e9rabit du secteur.<\/p>\n<p>\u00ab&nbsp;Le secteur est en train de passer \u00e0 un \u00e9cosyst\u00e8me PAM4 112G pour la commutation haute densit\u00e9, le traitement des paquets et l&rsquo;optique,&nbsp;\u00bb d\u00e9clare Bob Wheeler, Analyste en Chef R\u00e9seaux chez The Linley Group. \u00ab&nbsp;Le META-DX2L de Microchip est optimis\u00e9 pour r\u00e9pondre \u00e0 ces besoins en reliant les cartes de ligne aux tissus de commutation et aux optiques multi-d\u00e9bits pour assurer une connectivit\u00e9 100&nbsp;GbE, 400&nbsp;GbE et 800&nbsp;GbE.&nbsp;\u00bb<\/p>\n<p>Gr\u00e2ce \u00e0 sa bande passante haute densit\u00e9 de 1,6&nbsp;Tbits\/s, son encombrement r\u00e9duit, sa technologie SerDes PAM4 112G, et sa prise en charge de d\u00e9bits Ethernet allant de 1 \u00e0 800&nbsp;GbE, le PHY Ethernet META-DX2L de Microchip est un dispositif de classe de temp\u00e9rature industrielle, qui offre la polyvalence de connectivit\u00e9 n\u00e9cessaire pour maximiser la r\u00e9utilisation de conceptions dans des applications de type \u00ab&nbsp;retimer&nbsp;\u00bb (re-synchroniseur), \u00ab&nbsp;gearbox&nbsp;\u00bb (changeur de d\u00e9bit), \u00ab&nbsp;reverse gearbox&nbsp;\u00bb (changeur de d\u00e9bit inverse), ou multiplexeur 2 \u00e0&nbsp;1 sans collisions. Les fonctions \u00ab&nbsp;crosspoint&nbsp;\u00bb (croisement) et \u00ab&nbsp;gearbox&nbsp;\u00bb hautement configurables exploitent toute la bande passante E\/S d&rsquo;un commutateur pour permettre les connexions flexibles indispensables aux cartes multi-d\u00e9bits qui prennent en charge une large gamme de fibres optiques enfichables.<\/p>\n<p>Le SerDes PAM4 basse consommation du PHY lui permet de prendre en charge les d\u00e9bits d&rsquo;interface d&rsquo;infrastructure de nouvelle g\u00e9n\u00e9ration pour les centres de donn\u00e9es Cloud, les clusters de calcul IA\/ML, la 5G, et l&rsquo;infrastructure des op\u00e9rateurs de t\u00e9l\u00e9communications, qu\u2019il s\u2019agisse de c\u00e2bles en cuivre longue port\u00e9e \u00e0 connexion directe (DAC), de fonds de panier ou de fibres optiques enfichables.<\/p>\n<p>\u00ab&nbsp;Pour la g\u00e9n\u00e9ration 56G, nous avons introduit le premier PHY T\u00e9rabit du secteur, le META-DX1, et maintenant nous continuons avec une solution 112G tout aussi transformatrice, qui offre les capacit\u00e9s dont les concepteurs syst\u00e8me ont besoin pour r\u00e9soudre les nouveaux d\u00e9fis que posent aujourd\u2019hui les centres de donn\u00e9es Cloud, les r\u00e9seaux 5G et la mont\u00e9e en puissance du calcul IA\/ML,&nbsp;\u00bb a d\u00e9clar\u00e9 Babak Samimi, Vice-Pr\u00e9sident de la division Communications de Microchip. \u00ab&nbsp;En offrant jusqu&rsquo;\u00e0 1,6&nbsp;Tbits\/s de bande passante au sein d&rsquo;une architecture basse consommation, et ce dans le plus petit encombrement, le PHY META-DX2L double la bande passante des solutions pr\u00e9c\u00e9dentes sur le march\u00e9, tout en fixant une nouvelle norme d&rsquo;efficacit\u00e9 \u00e9nerg\u00e9tique.&nbsp;\u00bb<\/p>\n<p>Le META-DX2L est propos\u00e9 dans le plus petit bo\u00eetier du march\u00e9, 23&nbsp;x&nbsp;30&nbsp;mm, ce qui permet le gain de place n\u00e9cessaire pour proposer les densit\u00e9s de ports de carte de ligne que demandent les hyperscalers et les d\u00e9veloppeurs syst\u00e8me. Microchip fournit un ensemble complet de garanties de conception, de mod\u00e8les de r\u00e9f\u00e9rence et de cartes d&rsquo;\u00e9valuation, pour aider ses clients \u00e0 construire des syst\u00e8mes utilisant les dispositifs META-DX2L. En plus de la technologie Ethernet PHY, Microchip apporte \u00e9galement aux fournisseurs de syst\u00e8mes une solution compl\u00e8te comprenant des FPGA PolarFire, le PLL haute performance ZL30632, des oscillateurs, des r\u00e9gulateurs de tension et d&rsquo;autres composants qui ont \u00e9t\u00e9 pr\u00e9-valid\u00e9s au niveau syst\u00e8me avec le META-DX2L pour acc\u00e9l\u00e9rer la mise en production des conceptions.<\/p>\n<p>Les premiers dispositifs META-DX2L devraient \u00eatre \u00e9chantillonn\u00e9s au cours du 4\u00e8me trimestre 2021.<\/p>\n<p><a href=\"http:\/\/www.microchip.com\">www.microchip.com<\/a>.<\/p>\n<p>&nbsp;<\/p>\n","protected":false},"excerpt":{"rendered":"<p>Les routeurs, les commutateurs et les cartes de ligne ont besoin d&rsquo;une bande passante plus large, d&rsquo;une densit\u00e9 de ports et d&rsquo;une connectivit\u00e9 jusqu&rsquo;\u00e0 800 Gigabit Ethernet (GbE) pour g\u00e9rer l&rsquo;escalade du trafic des centres de donn\u00e9es induite par la 5G, les services cloud, et les applications d&rsquo;intelligence artificielle (IA) et d&rsquo;apprentissage automatique (ML pour Machine Learning). <\/p>\n","protected":false},"author":9,"featured_media":4032,"comment_status":"open","ping_status":"closed","sticky":false,"template":"","format":"standard","meta":{"_acf_changed":false,"footnotes":""},"categories":[881],"tags":[],"domains":[47],"ppma_author":[1141],"class_list":["post-4031","post","type-post","status-publish","format-standard","has-post-thumbnail","hentry","category-nouveaux-produits","domains-electronique-eci"],"acf":[],"yoast_head":"<title>Microchip d\u00e9voile le PHY Ethernet 1.6T le plus compact du marc...<\/title>\n<meta name=\"description\" content=\"Les routeurs, les commutateurs et les cartes de ligne ont besoin d&#039;une bande passante plus large, d&#039;une densit\u00e9 de ports et d&#039;une connectivit\u00e9 jusqu&#039;\u00e0 800...\" \/>\n<meta name=\"robots\" content=\"index, follow, max-snippet:-1, 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