{"id":399953,"date":"2022-10-23T19:21:09","date_gmt":"2022-10-23T17:21:09","guid":{"rendered":"https:\/\/www.eenewseurope.com\/?p=399953"},"modified":"2022-10-25T09:39:04","modified_gmt":"2022-10-25T07:39:04","slug":"tsmc-va-presenter-des-technologies-sub-1nm-avec-transistors-2d-a-liedm","status":"publish","type":"post","link":"https:\/\/www.ecinews.fr\/fr\/tsmc-va-presenter-des-technologies-sub-1nm-avec-transistors-2d-a-liedm\/","title":{"rendered":"TSMC va pr\u00e9senter des technologies sub-1nm avec transistors 2D"},"content":{"rendered":"<h2><span class=\"HwtZe\" lang=\"fr\"><span class=\"jCAhz\"><span class=\"ryNqvb\">Des chercheurs de la fonderie leader TSMC d\u00e9veloppent des transistors avec des tailles de caract\u00e9ristiques inf\u00e9rieures \u00e0 1 nm <\/span><\/span><\/span><\/h2>\n<p><span class=\"HwtZe\" lang=\"fr\"><span class=\"jCAhz\"><span class=\"ryNqvb\">pour miniaturiser encore plus les conceptions de puces et ont montr\u00e9 le premier transistor \u00e0 nanofeuilles avec une topologie de porte tout autour (GAA Gate all around)<\/span><\/span><\/span><\/p>\n<p><span class=\"HwtZe\" lang=\"fr\"><span class=\"jCAhz\"><span class=\"ryNqvb\"> Un volet de la prochaine conf\u00e9rence sur les dispositifs IEDM en d\u00e9cembre portera sur le d\u00e9veloppement de transistors 2D utilisant diff\u00e9rents mat\u00e9riaux. La conf\u00e9rence, qui c\u00e9l\u00e8bre maintenant ses 75 ans, offre une vision importante de la feuille de route pour la miniaturisation continue de la technologie des composants \u00e0 transistors. <\/span><\/span><\/span><\/p>\n<p><span class=\"HwtZe\" lang=\"fr\"><span class=\"jCAhz\"><span class=\"ryNqvb\">Les chercheurs de TSMC ont travaill\u00e9 avec des couches de dichalcog\u00e9nures de m\u00e9taux de transition (TMD) tels que MoS2 qui ne font qu&rsquo;un atome d&rsquo;\u00e9paisseur. Un d\u00e9fi majeur de ces mat\u00e9riaux est qu&rsquo;il est assez difficile de d\u00e9poser des couches di\u00e9lectriques sans trous d&rsquo;\u00e9pingle, ou des isolants, sur eux. Cela rend difficile leur incorporation dans l&#8217;empilement de mat\u00e9riaux qui forme une porte de transistor. <\/span><\/span><\/span><\/p>\n<p><span class=\"HwtZe\" lang=\"fr\"><span class=\"jCAhz\"><span class=\"ryNqvb\">L&rsquo;\u00e9quipe a int\u00e9gr\u00e9 des di\u00e9lectriques \u00e0 base d&rsquo;hafnium form\u00e9s par d\u00e9p\u00f4t de couche atomique avec le mat\u00e9riau TMD monocouche MoS2, pour construire un nFET \u00e0 grille sur le dessus avec une \u00e9paisseur di\u00e9lectrique physique de 3,4 nm et une \u00e9paisseur d&rsquo;oxyde \u00e9lectriquement \u00e9quivalente (EOT) d&rsquo;environ 1 nm.<\/span><\/span><\/span><\/p>\n<p><span class=\"HwtZe\" lang=\"fr\"><span class=\"jCAhz\"><span class=\"ryNqvb\">L&rsquo;oscillation sous-seuil (SS) est essentielle dans les transistors MOSFET, et les composants avaient une SS presque id\u00e9ale de &lt;70 mV\/d\u00e9c.<\/span><\/span><\/span><\/p>\n<p>&nbsp;<\/p>\n<ul>\n<li>\n<p class=\"title\"><a title=\"imec trace la voie pour aller au-del\u00e0 de 1nm\" href=\"https:\/\/www.ecinews.fr\/fr\/imec-trace-la-voie-pour-aller-au-dela-de-1nm\/\" target=\"_blank\" rel=\"noopener\">imec trace la voie pour aller au-del\u00e0 de 1nm<\/a><\/p>\n<\/li>\n<li>\n<p class=\"title\"><a title=\"Intel se restructure avec un mod\u00e8le de fonderie en interne\" href=\"https:\/\/www.ecinews.fr\/fr\/intel-se-restructure-avec-un-modele-de-fonderie-en-interne\/\" target=\"_blank\" rel=\"noopener\">Intel se restructure avec un mod\u00e8le de fonderie en interne<\/a><\/p>\n<\/li>\n<li><a href=\"https:\/\/www.eenewseurope.com\/en\/intel-charts-path-to-1nm-video\/\">Intel charts path to 1nm &#8211; video<\/a><\/li>\n<\/ul>\n<p><span class=\"HwtZe\" lang=\"fr\"><span class=\"jCAhz\"><span class=\"ryNqvb\">Une autre \u00e9quipe de TSMC a \u00e9galement d\u00e9velopp\u00e9 le premier transistor \u00e0 nanofeuilles 2D avec une architecture de grille tout autour (GAA). <\/span><\/span><\/span><\/p>\n<p><span class=\"HwtZe\" lang=\"fr\"><span class=\"jCAhz\"><span class=\"ryNqvb\">Les composants Nanosheet GAA sont consid\u00e9r\u00e9s comme le candidat le plus prometteur pour les architectures de composants de nouvelle g\u00e9n\u00e9ration car ils offrent un contr\u00f4le \u00e9lectrostatique am\u00e9lior\u00e9, un courant de commande relativement \u00e9lev\u00e9 et la possibilit\u00e9 de mettre en \u0153uvre des composants de largeurs variables. <\/span><\/span><\/span><\/p>\n<p><span class=\"HwtZe\" lang=\"fr\"><span class=\"jCAhz\"><span class=\"ryNqvb\">Actuellement, la r\u00e9duction de la longueur de grille et le contr\u00f4le \u00e9lectrostatique \u00e9lev\u00e9 proviennent de l&rsquo;amincissement du canal Si, mais \u00e0 l&rsquo;avenir, une r\u00e9duction extr\u00eame de la longueur de grille pourrait \u00eatre permise par l&rsquo;utilisation de TMD monocouches.<\/span><\/span><\/span><\/p>\n<p><span class=\"HwtZe\" lang=\"fr\"><span class=\"jCAhz\"><span class=\"ryNqvb\">Alors que les nanofeuilles de silicium int\u00e9gr\u00e9es \u00e0 la monocouche TMD comme mat\u00e9riau de canal sont prometteuses, les performances de ces dispositifs et leurs process de fabrication potentiels doivent encore \u00eatre explor\u00e9s plus avant. <\/span><\/span><\/span><\/p>\n<p><span class=\"HwtZe\" lang=\"fr\"><span class=\"jCAhz\"><span class=\"ryNqvb\">L&rsquo;\u00e9quipe a construit le tout premier FET \u00e0 nanofeuilles de MoS2 monocouche dans une configuration GAA. Avec une longueur de grille de 40 nm, le transistor pr\u00e9sentait une densit\u00e9 de courant d&rsquo;environ 410 \u00b5A\/\u00b5m \u00e0 1 V, obtenue avec un canal monocouche d&rsquo;environ 0,7 nm d&rsquo;\u00e9paisseur. <\/span><\/span><\/span><\/p>\n<p><span class=\"HwtZe\" lang=\"fr\"><span class=\"jCAhz\"><span class=\"ryNqvb\">Les chercheurs affirment qu&rsquo;un courant plus \u00e9lev\u00e9 peut \u00eatre obtenu en empilant plusieurs couches de canaux. <\/span><\/span><\/span><\/p>\n<p><span class=\"HwtZe\" lang=\"fr\"><span class=\"jCAhz\"><span class=\"ryNqvb\">Des contacts m\u00e9talliques \u00e0 faible r\u00e9sistance de connection aux mat\u00e9riaux 2D sont le goulot d&rsquo;\u00e9tranglement pour ces transistors. <\/span><\/span><\/span><\/p>\n<p><span class=\"HwtZe\" lang=\"fr\"><span class=\"jCAhz\"><span class=\"ryNqvb\">Bien que des progr\u00e8s aient \u00e9t\u00e9 r\u00e9alis\u00e9s avec les contacts de type n \u00e0 utiliser avec les nFET, les contacts de type p \u00e0 faible r\u00e9sistance \u00e0 utiliser avec les pFET sont plus difficiles en raison de l&rsquo;\u00e9lectro-thermodynamique<\/span><\/span><\/span><\/p>\n<p><span class=\"HwtZe\" lang=\"fr\"><span class=\"jCAhz\"><span class=\"ryNqvb\">Une \u00e9quipe dirig\u00e9e par TSMC a men\u00e9 des \u00e9tudes de mod\u00e9lisation et de simulation informatiques pour \u00e9tudier divers mat\u00e9riaux \u00e0 utiliser comme contacts de type p avec le mat\u00e9riau 2D WSe2. <\/span><\/span><\/span><\/p>\n<p><span class=\"HwtZe\" lang=\"fr\"><span class=\"jCAhz\"><span class=\"ryNqvb\">Il s&rsquo;agit notamment de contacts m\u00e9talliques utilisant un mat\u00e9riau tel que 1T-TiS2 et de contacts semi-m\u00e9talliques massifs utilisant divers mat\u00e9riaux, dont le Co3Sn2S2 a \u00e9t\u00e9 identifi\u00e9 comme exceptionnellement bon, avec une r\u00e9sistance de contact th\u00e9orique aussi faible que 20 \u03a9\u00b7\u03bcm.<\/span><\/span><\/span><\/p>\n<p><em>Paper #7.4, \u201cNearly Ideal Subthreshold Swing in Monolayer MoS2 Top-Gate nFETs with Scaled EOT of 1 nm,\u201d T-E Lee and Y-C Su et al, TSMC\/National Yang Ming Chiao Tung University\/National Applied Research Laboratories.<\/em><\/p>\n<p><em>Paper #34.5, \u201cFirst Demonstration of GAA Monolayer-MoS2 Nanosheet nFET with 410 \u03bcA\/\u03bcm ID at 1V VD at 40nm Gate Length,\u201d Y-Y. Chung et al, TSMC\/National Yang Ming Chiao Tung University\/National Applied Research Laboratories Taiwan<\/em><\/p>\n<p><em>Paper #28.1, \u201cComputational Screening and Multiscale Simulation of Barrier-Free Contacts for 2D Semiconductor pFETs,\u201d N. Yang et al, TSMC\/Penn State Univ.\/Univ. Florida\/Tohoku Univ.\/Rice Univ.\/Texas A&amp;M Univ.<\/em><\/p>\n<p><a href=\"http:\/\/www.ieee-iedm.org\">www.ieee-iedm.org<\/a><\/p>\n<h4>Related IEDM articles<\/h4>\n<ul>\n<li><a href=\"https:\/\/www.eenewseurope.com\/en\/europe-shows-2nm-quantum-technologies-at-iedm\/\">Europe shows 2nm, quantum technologies at IEDM<\/a><\/li>\n<li><a href=\"https:\/\/www.eenewseurope.com\/en\/iedm-samsung-makes-3nm-gate-all-around-cmos\/\">IEDM: Samsung makes 3nm gate-all-around CMOS<\/a><\/li>\n<\/ul>\n","protected":false},"excerpt":{"rendered":"<p>TSMC va pr\u00e9senter des technologies sub-1nm avec transistors 2D \u00e0 l&rsquo;IEDM<\/p>\n","protected":false},"author":34,"featured_media":399457,"comment_status":"closed","ping_status":"closed","sticky":true,"template":"","format":"standard","meta":{"_acf_changed":false,"footnotes":""},"categories":[886,26],"tags":[913,1558,1103],"domains":[47],"ppma_author":[1153,1138],"class_list":["post-399953","post","type-post","status-publish","format-standard","has-post-thumbnail","hentry","category-news-fr","category-technology-news","tag-materials-processes-fr","tag-semiconducteurs","tag-transistor","domains-electronique-eci"],"acf":[],"yoast_head":"<title>TSMC va pr\u00e9senter des technologies sub-1nm avec transistors 2D ...<\/title>\n<meta name=\"description\" content=\"Researchers at TSMC are developing 1nm 2D transistors and the first nanosheet transistor with a gate all around (GAA) topology\" \/>\n<meta name=\"robots\" content=\"index, follow, max-snippet:-1, max-image-preview:large, max-video-preview:-1\" \/>\n<link rel=\"canonical\" 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