{"id":398745,"date":"2022-10-12T19:08:52","date_gmt":"2022-10-12T17:08:52","guid":{"rendered":"https:\/\/www.eenewseurope.com\/?p=398745"},"modified":"2022-10-13T08:40:19","modified_gmt":"2022-10-13T06:40:19","slug":"le-processeur-securise-tesic-secure-made-in-france-utilise-risc-v","status":"publish","type":"post","link":"https:\/\/www.ecinews.fr\/fr\/le-processeur-securise-tesic-secure-made-in-france-utilise-risc-v\/","title":{"rendered":"Le processeur s\u00e9curis\u00e9 TESIC Secure made in France utilise RISC-V"},"content":{"rendered":"<h2>\u00a0<\/h2>\n<h2><span class=\"VIiyi\" lang=\"fr\"><span class=\"JLqJ4b\"><span class=\"Q4iAWc\">Le concepteur fran\u00e7ais de processeurs Tiempo Secure a d\u00e9velopp\u00e9 une IP s\u00e9curis\u00e9e bas\u00e9e sur le jeu d&rsquo;instructions ouvert RISC-V. <\/span><\/span><\/span><\/h2>\n<p><span class=\"VIiyi\" lang=\"fr\"><span class=\"JLqJ4b\"><span class=\"Q4iAWc\">L&rsquo;IP TESIC Secure Element utilise la sp\u00e9cification RISC-V 32 bits RV32IMCB pour adopter une architecture standard parall\u00e8lement \u00e0 son architecture CPU propri\u00e9taire existante. Cela facilitera l&rsquo;int\u00e9gration pour les d\u00e9veloppeurs qui peuvent d\u00e9sormais utiliser des outils de d\u00e9veloppement standard, rendant l&rsquo;int\u00e9gration de ses \u00e9l\u00e9ments de s\u00e9curit\u00e9 TESIC dans les conceptions de syst\u00e8mes sur une puce (SoC) plus rapide et plus facile. <\/span><\/span><\/span><\/p>\n<p><span class=\"VIiyi\" lang=\"fr\"><span class=\"JLqJ4b\"><span class=\"Q4iAWc\">Les \u00e9l\u00e9ments s\u00e9curis\u00e9s sont utilis\u00e9s dans les puces pour l&rsquo;authentification sur les r\u00e9seaux avec carte SIM int\u00e9gr\u00e9e (iSIM\/iUICC), le paiement (EMVCo), l&rsquo;identification gouvernementale ou priv\u00e9e, l&rsquo;authentification Web (FIDO 2), l&rsquo;acc\u00e8s aux voitures intelligentes et la communication avec les v\u00e9hicules autonomes (V2X HSM ).<\/span><\/span><\/span><\/p>\n<p><span class=\"VIiyi\" lang=\"fr\"><span class=\"JLqJ4b\"><span class=\"Q4iAWc\">La soci\u00e9t\u00e9 est bas\u00e9e \u00e0 Grenoble, en France, et devient \u00e9galement un membre strat\u00e9gique de RISC-V International, un comit\u00e9 qui aide \u00e0 guider le d\u00e9veloppement de la technologie.<\/span><\/span><\/span><\/p>\n<p>&nbsp;<\/p>\n<ul>\n<li>\n<p class=\"title\"><a title=\"ST et CAES font \u00e9quipe pour une puce spatiale octacore RISC-V\" href=\"https:\/\/www.ecinews.fr\/fr\/st-caes-font-equipe-pour-une-puce-spatiale-octacore-risc-v\/\">ST et CAES font \u00e9quipe pour une puce spatiale octacore RISC-V<\/a><\/p>\n<\/li>\n<li><a title=\"Microchip va d\u00e9velopper une nouvelle g\u00e9n\u00e9ration de processeurs 12 core RISC-V pour la NASA\" href=\"https:\/\/www.ecinews.fr\/fr\/microchip-va-developper-des-processeurs-risc-v-pour-la-nasa\/\" target=\"_blank\" rel=\"noopener\">Microchip va d\u00e9velopper une nouvelle g\u00e9n\u00e9ration de processeurs 12 core RISC-V pour la NASA<\/a><\/li>\n<li><a title=\"Le premier processeur RISC-V commence \u00e0 fonctionner en orbite\" href=\"https:\/\/www.ecinews.fr\/fr\/le-premier-processeur-risc-v-commence-a-fonctionner-en-orbite\/\" target=\"_blank\" rel=\"noopener\">Le premier processeur RISC-V commence \u00e0 fonctionner en orbite<\/a><\/li>\n<\/ul>\n<p><span class=\"VIiyi\" lang=\"fr\"><span class=\"JLqJ4b\"><span class=\"Q4iAWc\">\u00ab\u00a0Rejoindre RISC-V International repr\u00e9sente une \u00e9tape importante pour Tiempo Secure. Non seulement nous serons en mesure de continuer \u00e0 fournir des produits s\u00e9curis\u00e9s \u00e0 nos clients, mais nous facilitons d\u00e9sormais la mise en \u0153uvre de nos produits dans leurs propres syst\u00e8mes sur puce SoC et leurs logiciels. \u00ab\u00a0, a d\u00e9clar\u00e9 Serge Maginot, PDG de Tiempo Secure. <\/span><\/span><\/span><\/p>\n<p><span class=\"VIiyi\" lang=\"fr\"><span class=\"JLqJ4b\"><span class=\"Q4iAWc\">Comme Tiempo Secure est un expert en s\u00e9curit\u00e9 bien \u00e9tabli, ses produits TESIC Secure Element IP sont pr\u00eats pour la certification. L&rsquo;IP Tiempo Secure TESIC Secure element a \u00e9t\u00e9 int\u00e9gr\u00e9 dans des System-on-Chips qui ont pass\u00e9 la certification Common Criteria EAL 5+. De plus, Tiempo Secure s&rsquo;engage \u00e0 apporter un support \u00e9tendu \u00e0 ses int\u00e9grateurs en s&rsquo;assurant qu&rsquo;ils obtiennent la certification de s\u00e9curit\u00e9. <\/span><\/span><\/span><\/p>\n<ul>\n<li><a href=\"https:\/\/www.eenewseurope.com\/en\/tackling-the-challenges-of-risc-v\/\">Tackling the challenges of RISC-V<\/a><\/li>\n<li><a href=\"https:\/\/www.eenewseurope.com\/en\/first-native-risc-v-laptop-readies-for-market\/\">First native RISC-V laptop readies for market<\/a><\/li>\n<\/ul>\n<p><span class=\"VIiyi\" lang=\"fr\"><span class=\"JLqJ4b\"><span class=\"Q4iAWc\">Calista Redmond, PDG de RISC-V International, ajoute : \u00ab Nous sommes ravis de voir Tiempo Secure rejoindre RISC-V International. Leur exp\u00e9rience dans le d\u00e9veloppement de Secure Element IP, et plus globalement son expertise en mati\u00e8re de s\u00e9curit\u00e9, repr\u00e9senteront une partie prenante pr\u00e9cieuse pour notre organisation et nos membres.<\/span><\/span><\/span>\u00ab\u00a0<\/p>\n<p>&nbsp;<\/p>\n<p><a href=\"http:\/\/www.tiempo-secure.com\">www.tiempo-secure.com<\/a><\/p>\n<h4>Other RISC-V articles<\/h4>\n<ul>\n<li><a href=\"https:\/\/www.eenewseurope.com\/en\/risc-v-security-ip-for-chiplet-die-to-die-communication\/\">RISC-V security IP for chiplet die-to-die communication<\/a><\/li>\n<li><a href=\"https:\/\/www.eenewseurope.com\/en\/risc-v-chip-designed-with-open-source-tools\/\">RISC-V chip designed with open source tools<\/a><\/li>\n<li><a href=\"https:\/\/www.eenewseurope.com\/en\/andes-signs-crypto-quantique-for-risc-v-quantum-security\/\">Andes signs Crypto Quantique for RISC-V quantum security<\/a><\/li>\n<\/ul>\n<ul>\n<li><a href=\"https:\/\/www.eenewseurope.com\/en\/1400-risc-v-cores-for-on-chip-machine-learning\/\">1400 RISC-V cores for on-chip machine learning<\/a><\/li>\n<li><a href=\"https:\/\/www.eenewseurope.com\/en\/first-risc-v-chip-optimised-for-motor-control\/\">First RISC-V chip optimised for motor control<\/a><\/li>\n<li><a href=\"https:\/\/www.eenewseurope.com\/en\/risc-v-development-platform-for-edge-ai-chips\/\">Imagination teams for RISC-V development platform for edge<\/a><\/li>\n<\/ul>\n<p>&nbsp;<\/p>\n","protected":false},"excerpt":{"rendered":"<p>Le processeur s\u00e9curis\u00e9 TESIC Secure made in France utilise RISC-V<\/p>\n","protected":false},"author":34,"featured_media":398366,"comment_status":"closed","ping_status":"closed","sticky":true,"template":"","format":"standard","meta":{"_acf_changed":false,"footnotes":""},"categories":[886,18],"tags":[893,906,1674],"domains":[47],"ppma_author":[1153],"class_list":["post-398745","post","type-post","status-publish","format-standard","has-post-thumbnail","hentry","category-news-fr","category-business-news","tag-authentication-encryption-fr","tag-mpus-mcus-fr","tag-risc-v-2","domains-electronique-eci"],"acf":[],"yoast_head":"<title>Le processeur s\u00e9curis\u00e9 TESIC Secure made in France utilise RI...<\/title>\n<meta name=\"description\" content=\"Le fran\u00e7ais Tiempo Secure a d\u00e9velopp\u00e9 une IP s\u00e9curis\u00e9e bas\u00e9e sur le jeu d&#039;instructions ouvert RISC-V et a rejoint RISC-V International\" \/>\n<meta name=\"robots\" content=\"index, follow, max-snippet:-1, max-image-preview:large, max-video-preview:-1\" \/>\n<link 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