{"id":396367,"date":"2022-09-26T20:55:07","date_gmt":"2022-09-26T18:55:07","guid":{"rendered":"https:\/\/www.eenewseurope.com\/?p=396367"},"modified":"2022-09-27T09:45:28","modified_gmt":"2022-09-27T07:45:28","slug":"st-caes-font-equipe-pour-une-puce-spatiale-octacore-risc-v","status":"publish","type":"post","link":"https:\/\/www.ecinews.fr\/fr\/st-caes-font-equipe-pour-une-puce-spatiale-octacore-risc-v\/","title":{"rendered":"ST et CAES font \u00e9quipe pour une puce spatiale octacore RISC-V"},"content":{"rendered":"<p><span class=\"VIiyi\" lang=\"fr\"><span class=\"JLqJ4b\"><span class=\"Q4iAWc\">Le concepteur de syst\u00e8mes spatiaux CAES a con\u00e7u la premi\u00e8re puce tol\u00e9rante aux pannes \u00e0 huit c\u0153urs pouvant \u00eatre bas\u00e9e sur diff\u00e9rentes architectures, y compris RISC-V. <\/span><\/span><\/span><\/p>\n<p><span class=\"VIiyi\" lang=\"fr\"><span class=\"JLqJ4b\"><span class=\"Q4iAWc\">Le GR765 System-on-Chip (SoC) durci aux radiations sera le premier processeur s\u00e9lectionnable par l&rsquo;utilisateur pour l&rsquo;espace, permettant aux utilisateurs de choisir l&rsquo;ancien LEON5 SPARC V8 ou les nouveaux c\u0153urs de processeur NOEL-V RISC-V RV64. <\/span><\/span><\/span><\/p>\n<p><span class=\"VIiyi\" lang=\"fr\"><span class=\"JLqJ4b\"><span class=\"Q4iAWc\">Une puce de test \u00e0 c\u0153ur unique a \u00e9t\u00e9 fabriqu\u00e9e en Europe sur la technologie de processus FDSOI 28 nm de STMicroelectronics. <\/span><\/span><\/span><\/p>\n<p>&nbsp;<\/p>\n<h4>RISC-V dans l&rsquo;espace<\/h4>\n<ul>\n<li><a title=\"Microchip va d\u00e9velopper une nouvelle g\u00e9n\u00e9ration de processeurs 12 core RISC-V pour la NASA\" href=\"https:\/\/www.ecinews.fr\/fr\/microchip-va-developper-des-processeurs-risc-v-pour-la-nasa\/\" target=\"_blank\" rel=\"noopener\">Microchip va d\u00e9velopper une nouvelle g\u00e9n\u00e9ration de processeurs 12 core RISC-V pour la NASA<\/a><\/li>\n<li><a title=\"Le premier processeur RISC-V commence \u00e0 fonctionner en orbite\" href=\"https:\/\/www.ecinews.fr\/fr\/le-premier-processeur-risc-v-commence-a-fonctionner-en-orbite\/\" target=\"_blank\" rel=\"noopener\">Le premier processeur RISC-V commence \u00e0 fonctionner en orbite<\/a><\/li>\n<li class=\"title\"><a title=\"L\u2019UE lance son programme spatial int\u00e9gr\u00e9 \u00e0 13 milliards d\u2019euros\" href=\"https:\/\/www.ecinews.fr\/fr\/lue-lance-son-programme-spatial-integre-a-13-milliards-deuros\/\" target=\"_blank\" rel=\"noopener\">L\u2019UE lance son programme spatial int\u00e9gr\u00e9 \u00e0 13 milliards d\u2019euros<\/a><\/li>\n<li><a href=\"https:\/\/www.eenewseurope.com\/en\/16-core-risc-v-chip-for-space-designs\/\">16 core RISC-V chip for space designs<\/a><\/li>\n<\/ul>\n<p><span class=\"VIiyi\" lang=\"fr\"><span class=\"JLqJ4b\"><span class=\"Q4iAWc\">\u00ab CAES est ravi d&rsquo;annoncer le premier processeur spatial s\u00e9lectionnable par l&rsquo;utilisateur. Nous offrons \u00e0 nos clients des options pour s\u00e9lectionner la meilleure architecture en fonction de leurs besoins, tout en r\u00e9pondant aux besoins futurs de l&rsquo;industrie spatiale pour plus de calcul et un \u00e9cosyst\u00e8me transparent, ainsi qu&rsquo;en prenant en compte la taille, le poids et la puissance (SWaP) \u00bb, a d\u00e9clar\u00e9 Mike Elias, Senior Vice-pr\u00e9sident et directeur g\u00e9n\u00e9ral, Division des syst\u00e8mes spatiaux de CAES, qui a plusieurs contrats avec l&rsquo;Agence spatiale europ\u00e9enne (ESA) pour le d\u00e9veloppement de la puce.<\/span><\/span><\/span><\/p>\n<p><span class=\"VIiyi\" lang=\"fr\"><span class=\"JLqJ4b\"><span class=\"Q4iAWc\">CAES travaillera en \u00e9troite collaboration avec STMicroelectronics sur la fabrication et les qualifications des produits pour le GR765. <\/span><\/span><\/span><\/p>\n<p><span class=\"VIiyi\" lang=\"fr\"><span class=\"JLqJ4b\"><span class=\"Q4iAWc\">Sur la base du test de rayonnement sur la puce de d\u00e9monstration, CAES estime que la tol\u00e9rance SEU pour le produit GR765 est au moins cinq fois plus dure que les processeurs durcis aux rayonnements actuels. CAES mettra en \u0153uvre son approche h\u00e9rit\u00e9e de la tol\u00e9rance aux pannes, permettant aux logiciels de poursuivre l&rsquo;ex\u00e9cution de mani\u00e8re transparente en pr\u00e9sence d&rsquo;erreurs corrigibles, ainsi qu&rsquo;\u00e0 \u00e9tendre la tol\u00e9rance aux pannes aux p\u00e9riph\u00e9riques et aux biblioth\u00e8ques de logiciels. <\/span><\/span><\/span><\/p>\n<p>&nbsp;<\/p>\n<p><span class=\"VIiyi\" lang=\"fr\"><span class=\"JLqJ4b\"><span class=\"Q4iAWc\">Le GR765 permettra la r\u00e9utilisation des anciens logiciels LEON SPARC ou le d\u00e9veloppement de nouveaux logiciels pour l&rsquo;architecture NOEL-V RISC-V, offrant la possibilit\u00e9 d&rsquo;utiliser des logiciels et des outils d&rsquo;autres industries, y compris les outils de d\u00e9veloppement d&rsquo;Ashling. <\/span><\/span><\/span><\/p>\n<p><span class=\"VIiyi\" lang=\"fr\"><span class=\"JLqJ4b\"><span class=\"Q4iAWc\">\u00ab Nous sommes fiers de faire \u00e9quipe avec CAES sur leurs microprocesseurs de prochaine g\u00e9n\u00e9ration pour l&rsquo;espace. La combinaison des technologies \u00e9prouv\u00e9es SPARC et RISC-V avec la capacit\u00e9 et la maturit\u00e9 de la technologie 28 nm FDSOI pour l&rsquo;espace est une combinaison parfaite \u00bb, a d\u00e9clar\u00e9 Fran\u00e7ois Martin, responsable du d\u00e9veloppement commercial des ASIC pour l&rsquo;espace et la d\u00e9fense, groupe Microcontr\u00f4leur et num\u00e9rique, STMicroelectronics. \u00ab\u00a0En plus de la fabrication de silicium, ST assure la fabrication et la qualification des produits HiRel via sa cha\u00eene d&rsquo;approvisionnement de confiance dans ses usines de Crolles et de Rennes, en France.\u00a0\u00bb<\/span><\/span><\/span><\/p>\n<p><span class=\"VIiyi\" lang=\"fr\"><span class=\"JLqJ4b\"><span class=\"Q4iAWc\">Les contrats du programme Advanced Research in Telecommunications Systems\u00a0(ARTES) et Technology Development Element (TDE) permettront \u00e0 CAES d&rsquo;aller de l&rsquo;avant avec le d\u00e9veloppement et la fabrication du prototype GR765 sur cette technologie. <\/span><\/span><\/span><\/p>\n<p><span class=\"VIiyi\" lang=\"fr\"><span class=\"JLqJ4b\"><span class=\"Q4iAWc\">CAES a pr\u00e9c\u00e9demment re\u00e7u un financement de l&rsquo;Agence spatiale nationale su\u00e9doise (SNSA) dans le cadre du programme de technologie de soutien g\u00e9n\u00e9ral (GSTP) de l&rsquo;ESA pour le d\u00e9veloppement pr\u00e9liminaire des exigences du syst\u00e8me GR765.<\/span><\/span><\/span><\/p>\n<p><span class=\"VIiyi\" lang=\"fr\"><span class=\"JLqJ4b\"><span class=\"Q4iAWc\">\u00ab L&rsquo;ESA est fi\u00e8re de collaborer avec CAES dans le d\u00e9veloppement de cette prochaine g\u00e9n\u00e9ration de la technologie de traitement de donn\u00e9es qui est essentielle pour construire des syst\u00e8mes intelligents, puissants et s\u00e9curis\u00e9s dans l&rsquo;espace. Notre coop\u00e9ration renforcera la capacit\u00e9 de l&rsquo;Europe \u00e0 lancer et \u00e0 mener ses futures missions ambitieuses et nous placera en pole position pour faire progresser la norme technologique mondiale pour le traitement des donn\u00e9es dans l&rsquo;espace \u00bb, a d\u00e9clar\u00e9 Elodie Viau, directrice des t\u00e9l\u00e9communications et des applications int\u00e9gr\u00e9es \u00e0 l&rsquo;ESA. <\/span><\/span><\/span><\/p>\n<p><span class=\"VIiyi\" lang=\"fr\"><span class=\"JLqJ4b\"><span class=\"Q4iAWc\">\u00ab Le CAES GR765 r\u00e9pond aux demandes sans cesse croissantes du traitement des donn\u00e9es des charges utiles des t\u00e9l\u00e9communications, mais b\u00e9n\u00e9ficie \u00e9galement \u00e0 un large \u00e9ventail d&rsquo;autres applications critiques telles que l&rsquo;informatique embarqu\u00e9e \u00bb, a d\u00e9clar\u00e9 Michael Harverson, chef de la section du segment spatial \u00e0 l&rsquo;ESA. <\/span><\/span><\/span><\/p>\n<p><span class=\"VIiyi\" lang=\"fr\"><span class=\"JLqJ4b\"><span class=\"Q4iAWc\">Le programme ARTES (Advanced Research in Telecommunications Systems) de l&rsquo;ESA est unique en Europe et vise \u00e0 soutenir la comp\u00e9titivit\u00e9 de l&rsquo;industrie europ\u00e9enne et canadienne pour la plate-forme ou la charge utile d&rsquo;un satellite, d&rsquo;un terminal utilisateur ou d&rsquo;un syst\u00e8me complet de t\u00e9l\u00e9communications int\u00e9grant un r\u00e9seau avec son segment spatial . <\/span><\/span><\/span><\/p>\n<p>&nbsp;<\/p>\n<p><a href=\"http:\/\/www.caes.com\">www.caes.com<\/a>; <a href=\"https:\/\/artes.esa.int\/core-competitiveness\">artes.esa.int\/core-competitiveness<\/a><\/p>\n<h4>Autres articles sur ECI News<\/h4>\n<ul>\n<li>\n<div class=\"item header_news\">\n<div class=\"description\">\n<ul>\n<li class=\"title\"><a title=\"https:\/\/www.ecinews.fr\/fr\/arm-ibm-sassocient-pour-une-puce-ia-analogique-basse-puissance\/\" href=\"https:\/\/www.ecinews.fr\/fr\/arm-ibm-sassocient-pour-une-puce-ia-analogique-basse-puissance\/\" target=\"_blank\" rel=\"noopener\">ARM, IBM s\u2019associent pour une puce IA analogique basse puissance<\/a><\/li>\n<li>\n<p class=\"title\"><a title=\"Le march\u00e9 des semiconducteurs fonce vers sa plus grande r\u00e9cession depuis 2000\" href=\"https:\/\/www.ecinews.fr\/fr\/le-marche-des-semiconducteurs-fonce-vers-sa-plus-grande-recession-depuis-2000\/\" target=\"_blank\" rel=\"noopener\">Le march\u00e9 des semiconducteurs fonce vers sa plus grande r\u00e9cession depuis 2000<\/a><\/p>\n<\/li>\n<li>\n<p class=\"title\"><a title=\"La Linux Foundation Europe est lanc\u00e9e\" href=\"https:\/\/www.ecinews.fr\/fr\/la-linux-foundation-europe-est-lancee\/\" target=\"_blank\" rel=\"noopener\">La Linux Foundation Europe est lanc\u00e9e<\/a><\/p>\n<\/li>\n<\/ul>\n<\/div>\n<\/div>\n<\/li>\n<\/ul>\n<h4>\u00a0<\/h4>\n<h4>Other related articles<\/h4>\n<ul>\n<li><a href=\"https:\/\/www.eenewseurope.com\/en\/de-risc-updates-its-risc-v-space-project\/\">De-RISC updates its RISC-V space project<\/a><\/li>\n<li><a href=\"https:\/\/www.eenewseurope.com\/en\/first-steps-to-european-multicore-risc-v-chip-for-space\/\">First steps to European multicore RISC-V chip for space<\/a><\/li>\n<li><a href=\"https:\/\/www.eenewseurope.com\/en\/ashling-tools-for-risc-v-space-processor\/\">A<\/a><a href=\"https:\/\/www.eenewseurope.com\/en\/ashling-tools-for-risc-v-space-processor\/\">shling tools for RISC-V space processor<\/a><\/li>\n<li><a href=\"https:\/\/www.eenewseurope.com\/en\/eu-launches-its-e13bn-integrated-space-programme\/\">EU launches its \u20ac13bn integrated space programme<\/a><\/li>\n<\/ul>\n<p>&nbsp;<\/p>\n","protected":false},"excerpt":{"rendered":"<p>Le concepteur de syst\u00e8mes spatiaux CAES a con\u00e7u la premi\u00e8re puce tol\u00e9rante aux pannes \u00e0 huit c\u0153urs pouvant \u00eatre bas\u00e9e sur diff\u00e9rentes architectures, y compris RISC-V.<\/p>\n","protected":false},"author":34,"featured_media":396133,"comment_status":"closed","ping_status":"closed","sticky":true,"template":"","format":"standard","meta":{"_acf_changed":false,"footnotes":""},"categories":[886,26],"tags":[906,1674,1661],"domains":[47],"ppma_author":[1153],"class_list":["post-396367","post","type-post","status-publish","format-standard","has-post-thumbnail","hentry","category-news-fr","category-technology-news","tag-mpus-mcus-fr","tag-risc-v-2","tag-space-2","domains-electronique-eci"],"acf":[],"yoast_head":"<title>ST et CAES font \u00e9quipe pour une puce spatiale octacore RISC-V ...<\/title>\n<meta name=\"description\" content=\"CAES a con\u00e7u avec ST la premi\u00e8re puce tol\u00e9rante aux pannes \u00e0 huit c\u0153urs pouvant \u00eatre bas\u00e9e sur diff\u00e9rentes architectures, y compris RISC-V.\" \/>\n<meta name=\"robots\" content=\"index, follow, max-snippet:-1, max-image-preview:large, max-video-preview:-1\" \/>\n<link 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