{"id":387585,"date":"2022-06-23T19:21:18","date_gmt":"2022-06-23T17:21:18","guid":{"rendered":"https:\/\/www.eenewseurope.com\/?p=387585"},"modified":"2022-06-24T09:57:22","modified_gmt":"2022-06-24T07:57:22","slug":"puce-europeenne-risc-v-pour-kit-de-development-iot","status":"publish","type":"post","link":"https:\/\/www.ecinews.fr\/fr\/puce-europeenne-risc-v-pour-kit-de-development-iot\/","title":{"rendered":"Puce europ\u00e9enne RISC-V pour kit de d\u00e9veloppement IoT"},"content":{"rendered":"<p><span class=\"VIiyi\" lang=\"fr\"><span class=\"JLqJ4b\" data-language-for-alternatives=\"fr\" data-language-to-translate-into=\"en\" data-phrase-index=\"0\" data-number-of-phrases=\"1\"><span class=\"Q4iAWc\">Le kit de d\u00e9veloppement comprend le kit de d\u00e9veloppement logiciel (SDK) CORE-V avec un environnement de d\u00e9veloppement int\u00e9gr\u00e9 (IDE) Eclipse complet et des liens vers AWS IoT ExpressLink. Ce<\/span><\/span><\/span><span class=\"VIiyi\" lang=\"fr\"><span class=\"JLqJ4b\" data-language-for-alternatives=\"fr\" data-language-to-translate-into=\"en\" data-phrase-index=\"0\" data-number-of-phrases=\"1\"><span class=\"Q4iAWc\"> nouveau service alimente une gamme de modules mat\u00e9riels et inclut un logiciel valid\u00e9 par AWS qui connecte en toute s\u00e9curit\u00e9 les appareils au cloud. Le DevKit est destin\u00e9 au d\u00e9veloppement de logiciels pour les applications embarqu\u00e9es, bas\u00e9es sur l&rsquo;Internet des objets (IoT) et l&rsquo;intelligence artificielle (IA) et a \u00e9t\u00e9 lanc\u00e9 lors de l&rsquo;exposition Embedded World 2022 \u00e0 Nuremberg, en Allemagne.<\/span><\/span><\/span><\/p>\n<p><span class=\"VIiyi\" lang=\"fr\"><span class=\"JLqJ4b\" data-language-for-alternatives=\"fr\" data-language-to-translate-into=\"en\" data-phrase-index=\"0\" data-number-of-phrases=\"1\"><span class=\"Q4iAWc\">Le microcontr\u00f4leur CORE-V est bas\u00e9 sur le processeur RISC-V embarqu\u00e9 CV32E40P open source 32 bits. Celui-ci dispose d&rsquo;un pipeline en ligne \u00e0 quatre \u00e9tages qui impl\u00e9mente les extensions d&rsquo;instructions RV32IM[F]C RISC-V et est bas\u00e9 sur le c\u0153ur RI5CY de la plate-forme PULP (Parallel Ultra Low Power) d\u00e9velopp\u00e9 au Laboratoire des syst\u00e8mes int\u00e9gr\u00e9s (IIS) de l&rsquo;ETHZ. en Suisse et le groupe Energy-efficient Embedded Systems (EEES) de l&rsquo;Universit\u00e9 de Bologne. <\/span><\/span><\/span><\/p>\n<p><span class=\"VIiyi\" lang=\"fr\"><span class=\"JLqJ4b\" data-language-for-alternatives=\"fr\" data-language-to-translate-into=\"en\" data-phrase-index=\"0\" data-number-of-phrases=\"1\"><span class=\"Q4iAWc\">La puce est construite dans la technologie de process basse consommation GlobalFoundries 22FDX FD-SOI. La conception et la v\u00e9rification du processeur CV32E40P au c\u0153ur du MCU CORE-V ont impliqu\u00e9 des contributions cl\u00e9s d&rsquo;Imperas, Siemens EDA, SiLabs et bien d&rsquo;autres, en s&rsquo;appuyant sur la conception originale de l&rsquo;ETHZ. L&rsquo;int\u00e9gration num\u00e9rique et la conception back-end du microcontr\u00f4leur CORE-V ont \u00e9t\u00e9 g\u00e9r\u00e9es par QuickLogic et CMC Microsystems.<\/span><\/span><\/span><\/p>\n<h4>Related RISC-V articles<\/h4>\n<ul>\n<li>\n<p class=\"title\"><a href=\"https:\/\/www.ecinews.fr\/fr\/400-millions-pour-un-centre-de-conception-risc-v-a-barcelone\/\" target=\"_blank\" rel=\"noopener\">$400 millions pour un centre de conception RISC-V \u00e0 Barcelone<\/a><\/p>\n<\/li>\n<li>\n<p class=\"title\"><a href=\"https:\/\/www.ecinews.fr\/fr\/les-derniers-coeurs-risc-v-embarques-de-codasip-permettent-la-personnalisation-de-la-peripherie-de-lia-ml\/\" target=\"_blank\" rel=\"noopener\">Les derniers c\u0153urs RISC-V embarqu\u00e9s de Codasip permettent la personnalisation de la p\u00e9riph\u00e9rie de l\u2019IA\/ML<\/a><\/p>\n<\/li>\n<li>\n<p class=\"title\"><a href=\"https:\/\/www.ecinews.fr\/fr\/imagination-supprime-la-license-pour-ses-ips-en-instituant-un-open-access\/\" target=\"_blank\" rel=\"noopener\">Imagination supprime la license pour ses IPs en instituant un Open Access<\/a><\/p>\n<\/li>\n<li><a href=\"https:\/\/www.eenewseurope.com\/en\/core-v-chassis-soc-open-source-project-calls-for-participation\/\">CORE-V Chassis SoC open source project calls for participation<\/a><\/li>\n<li><a href=\"https:\/\/www.eenewsembedded.com\/en\/free-iss-for-risc-v-core-v-developers-in-the-openhw-ecosystem\/\">Free ISS for RISC-V CORE-V developers in OpenHW<\/a><\/li>\n<li><a href=\"https:\/\/www.eenewseurope.com\/en\/risc-v-app-provides-verification-toolchain\/\">RISC-V app provides verification toolchain<\/a><\/li>\n<\/ul>\n<p><span class=\"VIiyi\" lang=\"fr\"><span class=\"JLqJ4b\" data-language-for-alternatives=\"fr\" data-language-to-translate-into=\"en\" data-phrase-index=\"0\" data-number-of-phrases=\"1\"><span class=\"Q4iAWc\"> Le microcontr\u00f4leur comprend \u00e9galement l&rsquo;eFPGA de QuickLogic, con\u00e7u pour acc\u00e9l\u00e9rer l&rsquo;IA\/l&rsquo;apprentissage automatique (ML) et d&rsquo;autres charges de travail intensives en calcul \u00e0 partir du processeur CV32E40P. <\/span><\/span><\/span><\/p>\n<p><span class=\"VIiyi\" lang=\"fr\"><span class=\"JLqJ4b\" data-language-for-alternatives=\"fr\" data-language-to-translate-into=\"en\" data-phrase-index=\"0\" data-number-of-phrases=\"1\"><span class=\"Q4iAWc\">\u00ab\u00a0L&rsquo;\u00e9norme potentiel des applications IoT n\u00e9cessite de nouvelles fa\u00e7ons de penser la conception, et la communaut\u00e9 open source fournit du mat\u00e9riel, des logiciels et des outils de d\u00e9veloppement pour acc\u00e9l\u00e9rer l&rsquo;innovation\u00a0\u00bb, a d\u00e9clar\u00e9 Rick O&rsquo;Connor, pr\u00e9sident et chef de la direction d&rsquo;OpenHW Group. \u00ab\u00a0C&rsquo;est vraiment inspirant de voir un effort d&rsquo;ing\u00e9nierie collaborative mondial aussi coh\u00e9rent pour d\u00e9velopper des blocs de construction open source permettant des conceptions de microcontr\u00f4leurs int\u00e9gr\u00e9s.\u00a0\u00bb<\/span><\/span><\/span><\/p>\n<p><span class=\"VIiyi\" lang=\"fr\"><span class=\"JLqJ4b\" data-language-for-alternatives=\"fr\" data-language-to-translate-into=\"en\" data-phrase-index=\"0\" data-number-of-phrases=\"1\"><span class=\"Q4iAWc\">Le kit de d\u00e9veloppement est utilis\u00e9 par les membres du groupe OpenHW pour \u00e9muler un ensemble de capteurs de stations m\u00e9t\u00e9orologiques situ\u00e9s dans le hall d&rsquo;exposition ( \u00e0 Embedded World Nuremberg) ainsi qu&rsquo;\u00e0 divers endroits dans le monde. La d\u00e9monstration, impliquant plus d&rsquo;une douzaine de kits sur divers stands d&rsquo;exposition, met en \u00e9vidence l&rsquo;interconnexion des capteurs IoT et l&rsquo;application vers AWS, avec des lectures de temp\u00e9rature locales sur la carte CORE-V MCU DevKit NexysA7. <\/span><\/span><\/span><\/p>\n<p><span class=\"VIiyi\" lang=\"fr\"><span class=\"JLqJ4b\" data-language-for-alternatives=\"fr\" data-language-to-translate-into=\"en\" data-phrase-index=\"0\" data-number-of-phrases=\"1\"><span class=\"Q4iAWc\">Le d\u00e9veloppement du SDK DevKit a \u00e9t\u00e9 dirig\u00e9 par Ashling, qui fournit \u00e9galement des outils de d\u00e9veloppement logiciel RISC-V pour MIPS et Intel. <\/span><\/span><\/span><\/p>\n<p><span class=\"VIiyi\" lang=\"fr\"><span class=\"JLqJ4b\" data-language-for-alternatives=\"fr\" data-language-to-translate-into=\"en\" data-phrase-index=\"0\" data-number-of-phrases=\"1\"><span class=\"Q4iAWc\">Le SDK OpenHW contient un IDE, un d\u00e9bogueur, un compilateur GCC (fourni par Embecosm), le syst\u00e8me d&rsquo;exploitation en temps r\u00e9el FreeRTOS d&rsquo;Amazon et la connectivit\u00e9 AWS IoT ExpressLink via la radio WiFi bas\u00e9e sur RISC-V d&rsquo;Espressif. Le projet met en \u00e9vidence le\u00a0d\u00e9veloppement collaboratif open-source de l&rsquo;IP de processeur CORE-V de qualit\u00e9 industrielle avec le mat\u00e9riel et les logiciels de support par un large \u00e9ventail de membres au sein de la communaut\u00e9 OpenHW.<\/span><\/span><\/span><\/p>\n<p><span class=\"VIiyi\" lang=\"fr\"><span class=\"JLqJ4b\" data-language-for-alternatives=\"fr\" data-language-to-translate-into=\"en\" data-phrase-index=\"0\" data-number-of-phrases=\"1\"><span class=\"Q4iAWc\">Embecosm au Royaume-Uni dirige les projets du groupe de travail OpenHW SW, y compris les outils de compilateur GCC pour les c\u0153urs CORE-V et le MCU, tandis qu&rsquo;Ashling a dirig\u00e9 le d\u00e9veloppement du SDK CORE-V bas\u00e9 sur l&rsquo;IDE Eclipse, OpenOCD pour le d\u00e9bogage et les exemples de programmes. <\/span><\/span><\/span><\/p>\n<p><span class=\"VIiyi\" lang=\"fr\"><span class=\"JLqJ4b\" data-language-for-alternatives=\"fr\" data-language-to-translate-into=\"en\" data-phrase-index=\"0\" data-number-of-phrases=\"1\"><span class=\"Q4iAWc\">Imperas, \u00e9galement bas\u00e9 au Royaume-Uni, a publi\u00e9 un simulateur gratuit pour le MCU CORE-V. Le riscvOVPsimCOREV est bas\u00e9 sur les mod\u00e8les de r\u00e9f\u00e9rence Imperas RISC-V utilis\u00e9s dans la v\u00e9rification de CV32E40P, comme point de d\u00e9part pour les t\u00e2ches de d\u00e9veloppement logiciel.<\/span><\/span><\/span><\/p>\n<p><span class=\"VIiyi\" lang=\"fr\"><span class=\"JLqJ4b\" data-language-for-alternatives=\"fr\" data-language-to-translate-into=\"en\" data-phrase-index=\"0\" data-number-of-phrases=\"1\"><span class=\"Q4iAWc\">La fabrication et l&rsquo;exp\u00e9dition de la campagne d&rsquo;acc\u00e8s anticip\u00e9 CORE-V MCU DevKit sont coordonn\u00e9es par GroupGets. Les quantit\u00e9s de DevKit CORE-V MCU \u00e0 acc\u00e8s anticip\u00e9 sont limit\u00e9es et peuvent \u00eatre r\u00e9serv\u00e9es <a href=\"https:\/\/groupgets.com\/campaigns\/1040-core-v-mcu-devkit\" target=\"_blank\" rel=\"noopener\">ici<\/a>. <\/span><\/span><\/span><\/p>\n<p><span class=\"VIiyi\" lang=\"fr\"><span class=\"JLqJ4b\" data-language-for-alternatives=\"fr\" data-language-to-translate-into=\"en\" data-phrase-index=\"0\" data-number-of-phrases=\"1\"><span class=\"Q4iAWc\">Le <a href=\"http:\/\/www.openhwgroup.org\/\" target=\"_blank\" rel=\"noopener\">groupe OpenHW<\/a> est bas\u00e9 au Canada et fournit une infrastructure pour h\u00e9berger des d\u00e9veloppements mat\u00e9riels open source de haute qualit\u00e9 et comprend un groupe de travail Cores pour d\u00e9velopper l&rsquo;IP open source pour la famille CORE-V de processeurs RISC-V open source.<\/span><\/span><\/span><\/p>\n<p>&nbsp;<\/p>\n","protected":false},"excerpt":{"rendered":"<p>Le groupe OpenHW a lanc\u00e9 un kit de d\u00e9veloppement RISC-V open source bas\u00e9 sur le microcontr\u00f4leur europ\u00e9en CORE-V et une conception de carte de circuit imprim\u00e9 (PCB) ouverte qui prend en charge Amazon Web Services (AWS) pour l&rsquo;Internet des objets (IoT)<\/p>\n","protected":false},"author":34,"featured_media":387275,"comment_status":"closed","ping_status":"closed","sticky":false,"template":"","format":"standard","meta":{"_acf_changed":false,"footnotes":""},"categories":[881,26],"tags":[894,1604,895,906],"domains":[47],"ppma_author":[1153],"class_list":["post-387585","post","type-post","status-publish","format-standard","has-post-thumbnail","hentry","category-nouveaux-produits","category-technology-news","tag-boards-embedded-cards-fr","tag-development-kits","tag-developmentkits-fr","tag-mpus-mcus-fr","domains-electronique-eci"],"acf":[],"yoast_head":"<title>Puce europ\u00e9enne RISC-V pour kit de d\u00e9veloppement IoT ...<\/title>\n<meta name=\"description\" content=\"Le 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