{"id":385947,"date":"2022-06-02T19:11:52","date_gmt":"2022-06-02T17:11:52","guid":{"rendered":"https:\/\/www.eenewseurope.com\/?p=385947"},"modified":"2022-06-03T15:32:24","modified_gmt":"2022-06-03T13:32:24","slug":"cea-leti-intel-developpent-une-technique-dauto-assemblage-puce-a-wafer","status":"publish","type":"post","link":"https:\/\/www.ecinews.fr\/fr\/cea-leti-intel-developpent-une-technique-dauto-assemblage-puce-a-wafer\/","title":{"rendered":"Le CEA-Leti et Intel d\u00e9veloppent une technique d&rsquo;auto-assemblage puce-\u00e0-wafer"},"content":{"rendered":"<p><span class=\"VIiyi\" lang=\"fr\"><span class=\"JLqJ4b\" data-language-for-alternatives=\"fr\" data-language-to-translate-into=\"en\" data-phrase-index=\"0\" data-number-of-phrases=\"1\"><span class=\"Q4iAWc\">La technique peut augmenter la pr\u00e9cision de l&rsquo;alignement et augmenter le d\u00e9bit de fabrication de plusieurs milliers de puces par heure en utilisant une gouttelette d&rsquo;eau pour aligner les puces sur un wafer cible. <\/span><\/span><\/span><\/p>\n<p><span class=\"VIiyi\" lang=\"fr\"><span class=\"JLqJ4b\" data-language-for-alternatives=\"fr\" data-language-to-translate-into=\"en\" data-phrase-index=\"0\" data-number-of-phrases=\"1\"><span class=\"Q4iAWc\">Le process de liaison hybride D2W est consid\u00e9r\u00e9 comme essentiel pour combiner la m\u00e9moire, le HPC et les chiplets photoniques sur un substrat de wafer, mais il est beaucoup plus complexe que la liaison wafer \u00e0 wafer, avec une pr\u00e9cision d&rsquo;alignement inf\u00e9rieure et un d\u00e9bit d&rsquo;assemblage de puce inf\u00e9rieur. <\/span><\/span><\/span><\/p>\n<p><span class=\"VIiyi\" lang=\"fr\"><span class=\"JLqJ4b\" data-language-for-alternatives=\"fr\" data-language-to-translate-into=\"en\" data-phrase-index=\"0\" data-number-of-phrases=\"1\"><span class=\"Q4iAWc\">Le CEA-Leti d\u00e9veloppe depuis plusieurs ann\u00e9es une m\u00e9thode d&rsquo;auto-assemblage, avec pour objectif d&rsquo;augmenter sensiblement le d\u00e9bit et la pr\u00e9cision de placement. <\/span><\/span><\/span><\/p>\n<p><span class=\"VIiyi\" lang=\"fr\"><span class=\"JLqJ4b\" data-language-for-alternatives=\"fr\" data-language-to-translate-into=\"en\" data-phrase-index=\"0\" data-number-of-phrases=\"1\"><span class=\"Q4iAWc\">\u00ab\u00a0Le d\u00e9bit \u00e0 l&rsquo;\u00e9chelle commerciale avec l&rsquo;auto-assemblage D2W pr\u00e9sente deux d\u00e9fis principaux li\u00e9s \u00e0 la manipulation des puces\u00a0\u00bb, a d\u00e9clar\u00e9 Emilie Bourjot, chef de projet d&rsquo;int\u00e9gration 3D au CEA-Leti. \u00ab Si le process d&rsquo;auto-assemblage est combin\u00e9 avec un outil de pick-and-place, le d\u00e9bit peut \u00eatre augment\u00e9 en r\u00e9duisant le temps d&rsquo;alignement, puisque l&rsquo;alignement fin est effectu\u00e9 par la gouttelette. Lorsque l&rsquo;auto-assemblage est combin\u00e9 \u00e0 une solution collective de manipulation des puces, le d\u00e9bit est augment\u00e9 par le fait que toutes les puces sont coll\u00e9es ensemble en m\u00eame temps sans aucun placement de haute pr\u00e9cision \u00e0 tout moment dans le flux du process. <\/span><\/span><\/span><\/p>\n<p><span class=\"VIiyi\" lang=\"fr\"><span class=\"JLqJ4b\" data-language-for-alternatives=\"fr\" data-language-to-translate-into=\"en\" data-phrase-index=\"0\" data-number-of-phrases=\"1\"><span class=\"Q4iAWc\">L&rsquo;optimisation des proc\u00e9d\u00e9s est \u00e9galement une partie importante de ce travail pour augmenter la maturit\u00e9 des proc\u00e9d\u00e9s et cibler les exigences industrielles. \u00ab\u00a0Avec de telles performances d&rsquo;alignement et de d\u00e9bit, c&rsquo;est d\u00e9finitivement une \u00e9tape prometteuse alliant la magie de la physique et une simple goutte d&rsquo;eau\u00a0\u00bb, a d\u00e9clar\u00e9 Bourjot. Un article pr\u00e9sent\u00e9 cette semaine \u00e0 la Conf\u00e9rence sur les composants et la technologie \u00e9lectroniques (ECTC) de 2022 d\u00e9crit la technique qui utilise les forces capillaires qui d\u00e9coulent du principe de minimisation de la surface et s&rsquo;exercent par la tension superficielle dans le cas d&rsquo;un liquide.<\/span><\/span><\/span><\/p>\n<p><span class=\"VIiyi\" lang=\"fr\"><span class=\"JLqJ4b\" data-language-for-alternatives=\"fr\" data-language-to-translate-into=\"en\" data-phrase-index=\"0\" data-number-of-phrases=\"1\"><span class=\"Q4iAWc\">D&rsquo;un point de vue macroscopique, le liquide tend \u00e0 minimiser son interface liquide\/air pour atteindre un \u00e9tat d&rsquo;\u00e9quilibre avec une \u00e9nergie minimale. Ce m\u00e9canisme permet l&rsquo;auto-alignement de la puce sur son site de collage. Le liquide choisi comme vecteur de r\u00e9alignement doit pr\u00e9senter une tension superficielle \u00e9lev\u00e9e et doit \u00eatre compatible avec un collage direct. La plupart des liquides ont une tension superficielle comprise entre 20 et 50 mN\/m, \u00e0 l&rsquo;exception de l&rsquo;eau qui pr\u00e9sente une tension superficielle de 72,1 mN\/m, ce qui en fait un excellent candidat pour les processus d&rsquo;auto-assemblage par collage hydrophile dans lesquels l&rsquo;eau est d\u00e9j\u00e0 un param\u00e8tre cl\u00e9 du m\u00e9canisme.<\/span><\/span><\/span><\/p>\n<p><span class=\"VIiyi\" lang=\"fr\"><span class=\"JLqJ4b\" data-language-for-alternatives=\"fr\" data-language-to-translate-into=\"en\" data-phrase-index=\"0\" data-number-of-phrases=\"1\"><span class=\"Q4iAWc\">Le CEA-Leti a d\u00e9velopp\u00e9 en interne un syst\u00e8me D2W qui a montr\u00e9 un d\u00e9salignement moyen inf\u00e9rieur \u00e0 150 nm pour une large gamme de dimensions de puces (8&#215;8 mm\u00b2, 2,7&#215;2,7 mm2, 1,3&#215;11,8 mm2 et 2,2&#215;11,8 mm2). Cela se compare \u00e0 un alignement de 1 \u00b5m pour un post-bonding d&rsquo;outil pick-and-place et au meilleur des cas de 700 nm, tandis qu&rsquo;un processus d&rsquo;auto-alignement offre un alignement inf\u00e9rieur \u00e0 500 nm et m\u00eame inf\u00e9rieur \u00e0 200 nm, post-bonding. <\/span><\/span><\/span><\/p>\n<p><span class=\"VIiyi\" lang=\"fr\"><span class=\"JLqJ4b\" data-language-for-alternatives=\"fr\" data-language-to-translate-into=\"en\" data-phrase-index=\"0\" data-number-of-phrases=\"1\"><span class=\"Q4iAWc\">\u00ab Comme il n&rsquo;existe aucun outil industriel pour l&rsquo;approche de l&rsquo;auto-assemblage, l&rsquo;\u00e9quipe a fabriqu\u00e9 son propre outil permettant un auto-assemblage collectif. Le contr\u00f4le manuel du processus \u00e0 faible reproductibilit\u00e9 a n\u00e9anmoins atteint un alignement de 500 nm et moins, ce qui sugg\u00e8re fortement qu&rsquo;un outil industriel d\u00e9di\u00e9 \u00e0 ce processus offrirait une reproductibilit\u00e9, une robustesse et une pr\u00e9cision sup\u00e9rieures \u00bb, a d\u00e9clar\u00e9 le CEA-Leti.<\/span><\/span><\/span><\/p>\n<p><span class=\"VIiyi\" lang=\"fr\"><span class=\"JLqJ4b\" data-language-for-alternatives=\"fr\" data-language-to-translate-into=\"en\" data-phrase-index=\"0\" data-number-of-phrases=\"1\"><span class=\"Q4iAWc\">L&rsquo;objectif du document est d&rsquo;encourager les fabricants d&rsquo;\u00e9quipements d&rsquo;assemblage \u00e0 adopter la technologie. \u00ab\u00a0De nombreux aspects de l&rsquo;auto-assemblage doivent encore \u00eatre explor\u00e9s et de grandes am\u00e9liorations ne seront possibles que lorsque les fournisseurs d&rsquo;outils d\u00e9velopperont (un) outil adapt\u00e9 pour automatiser ce processus\u00a0\u00bb, ont d\u00e9clar\u00e9 les chercheurs.<\/span><\/span><\/span><\/p>\n<p>&nbsp;<\/p>\n<p><a href=\"http:\/\/www.leti-cea.com\">www.leti-cea.com<\/a>; <a href=\"http:\/\/www.intel.com\">www.intel.com<\/a><\/p>\n<h4>Related articles<\/h4>\n<ul>\n<li><a href=\"https:\/\/www.eenewseurope.com\/en\/system-in-package-consortium-for-heterogeneous-chiplets\/\">System-in-package consortium for heterogeneous chiplets<\/a><\/li>\n<li><a href=\"https:\/\/www.eenewseurope.com\/en\/intel-to-expand-in-france-and-italy-reports\/\">Intel to expand assembly in France and Italy \u2013 reports<\/a><\/li>\n<li><a href=\"https:\/\/www.eenewseurope.com\/en\/nexperia-spins-out-its-semiconductor-equipment-business\/\">Nexperia spins out its semiconductor equipment business<\/a><\/li>\n<\/ul>\n<p>&nbsp;<\/p>\n<p>&nbsp;<\/p>\n<p>&nbsp;<\/p>\n","protected":false},"excerpt":{"rendered":"<p>Le laboratoire de recherche fran\u00e7ais CEA-Leti et Intel ont optimis\u00e9 un process d&rsquo;auto-assemblage \u00e0 liaison directe hybride qui pourrait stimuler l&rsquo;utilisation de la liaison puce-\u00e0-wafer (D2W).<\/p>\n","protected":false},"author":34,"featured_media":385923,"comment_status":"closed","ping_status":"closed","sticky":false,"template":"","format":"standard","meta":{"_acf_changed":false,"footnotes":""},"categories":[886,26],"tags":[913],"domains":[47],"ppma_author":[1153],"class_list":["post-385947","post","type-post","status-publish","format-standard","has-post-thumbnail","hentry","category-news-fr","category-technology-news","tag-materials-processes-fr","domains-electronique-eci"],"acf":[],"yoast_head":"<title>Le CEA-Leti et Intel d\u00e9veloppent une technique d&#039;auto-assembla...<\/title>\n<meta name=\"description\" content=\"CEA-Leti and Intel have optimized a hybrid direct-bonding, self-assembly process that could boost the use of die-to-wafer (D2W) bonding.\" \/>\n<meta name=\"robots\" content=\"index, follow, max-snippet:-1, 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