{"id":38558,"date":"2020-12-21T16:16:41","date_gmt":"2020-12-21T16:16:41","guid":{"rendered":"https:\/\/\/coeur-de-processeur-1ghz-risc-v-ne-consommant-que-10mw\/"},"modified":"2020-12-21T16:16:41","modified_gmt":"2020-12-21T16:16:41","slug":"coeur-de-processeur-1ghz-risc-v-ne-consommant-que-10mw","status":"publish","type":"post","link":"https:\/\/www.ecinews.fr\/fr\/coeur-de-processeur-1ghz-risc-v-ne-consommant-que-10mw\/","title":{"rendered":"Coeur de Processeur 1GHz RISC-V ne consommant que 10mW"},"content":{"rendered":"

Le noyau a \u00e9t\u00e9 d\u00e9velopp\u00e9 par Micro Magic Inc. (Sunnyvale, Californie), une soci\u00e9t\u00e9 de services de conception de processeurs existante de longue date et d\u00e9veloppeur d’outils EDA. La soci\u00e9t\u00e9 avait d\u00e9j\u00e0 affirm\u00e9 que sa conception \u00e9tait le processeur RISC-V 64 bits le plus rapide (voir <\/span><\/span><\/span>EDA company claims world’s fastest 64bit RISC-V core<\/a> ).<\/span><\/span><\/span><\/p>\n

Mais dans une interview avec eeNews Europe, Mark Santoro, PDG de Micro Magic, a d\u00e9clar\u00e9 que le c\u0153ur du processeur avait \u00e9galement \u00e9t\u00e9 con\u00e7u pour pouvoir fonctionner jusqu’\u00e0 une tension minimale de 350 mV, soit aux environs de la tension de seuil du processus de fabrication. (voir l’interview du PDG: <\/span><\/span><\/span> CEO interview: Silicon Valley is still the place where the magic happens<\/a>). Cela permet de sacrifier les performances quand elles ne sont pas c\u00e9cessaires pour r\u00e9aliser des \u00e9conomies d’\u00e9nergie consid\u00e9rables.<\/span><\/span><\/span><\/p>\n

\u00c0 1,1 V, le c\u0153ur RISC-V fonctionne \u00e0 une fr\u00e9quence d’horloge de 5,1 GHz et consomme environ 500 mW. \u00c0 350 mV, le c\u0153ur peut toujours fonctionner \u00e0 une fr\u00e9quence d’horloge de 1 GHz et ne consomme que 10 mW.<\/span><\/span><\/span><\/p>\n

Micro Magic a choisi le benchmark CoreMarks du Embedded Microprocessor Benchmark Consortium (EEMBC) comme mesure de performance. \u00c0 5,1 GHz, le processeur atteint 13333 CoreMarks et \u00e0 1 GHz, il atteint 2500 CoreMarks, ce qui donne des chiffres de 26,6k CoreMarks \/ W \u00e0 5,1 GHz et 250k CoreMarks \/ W \u00e0 1 GHz. Cela signifie qu’en r\u00e9duisant la tension \u00e0 un tiers et la fr\u00e9quence d’horloge d’un facteur cinq, une augmentation du rendement \u00e9nerg\u00e9tique de plus de 9 fois peut \u00eatre obtenue. <\/span><\/span><\/span><\/p>\n

Micro Magic a r\u00e9alis\u00e9 ces mesures sur du silicium r\u00e9el fabriqu\u00e9 en fonderie sur des plaquettes multi-projets. Et aucun \u00ab\u00a0binning\u00a0\u00bb de puces n’a \u00e9t\u00e9 utilis\u00e9 dans l’analyse comparative, de sorte que la m\u00eame puce peut atteindre \u00e0 la fois 5,1 GHz (500 mW) \u00e0 1,1 V et 1 GHz (10 mW) \u00e0 350 mV. Cela ouvre la perspective d’une mise \u00e0 l’\u00e9chelle dynamique des performances et de la puissance. <\/span><\/span><\/span><\/p>\n

\u00e0 suivre: Quelle fonderie? quel processus?<\/span><\/span><\/span><\/p>\n

 <\/p>\n

\n

 <\/p>\n

Cependant, la soci\u00e9t\u00e9 n’a pas voulu r\u00e9v\u00e9ler quel proc\u00e9d\u00e9 de fabrication ou quel fabricant de fonderie ont \u00e9t\u00e9 utilis\u00e9s. La soci\u00e9t\u00e9 a d\u00e9clar\u00e9 que la conception utilise un processus FinFET et qu’elle a examin\u00e9 les kits de conception physique (PDK) de trois grandes fonderies \u00e0 la recherche de la compatibilit\u00e9 la plus large avant d’en s\u00e9lectionner une pour la fabrication.<\/span><\/span><\/span><\/p>\n

Le processus est susceptible d’\u00eatre quelque part entre 20 nm et 10 nm et provient probabement de l’une des fonderies suivantes: Globalfoundries, Samsung, SMIC et TSMC. Intel fabrique \u00e9galement en utilisant des processus FinFET, mais il semble qu’il a abandonn\u00e9 l’activit\u00e9 de fonderie.<\/span><\/span><\/span><\/p>\n

Le chinois SMIC a commenc\u00e9 la production de masse \u00e0 14 nm au 4T19 et la soci\u00e9t\u00e9 annonce sp\u00e9cifiquement la capacit\u00e9 de prendre en charge des tensions de travail ultra-basses et de faire fonctionner des c\u0153urs avec trois tensions de seuil diff\u00e9rentes.<\/span><\/span><\/span><\/p>\n

Santoro souligne \u00e9galement que la conception de Micro Magic comble \u00e0 la fois les exigences de calcul haute performance des centres de donn\u00e9es et les besoins de faible consommation d’\u00e9nergie des smartphones. Ce sont les principaux domaines d’application pour les soci\u00e9t\u00e9s de puces utilisant des processus de fabrication de pointe en 7 nm et 5 nm. Cependant, l’architecture RISC-V open source n’a pas encore fait de progr\u00e8s significatifs dans l’un ou l’autre de ces secteurs d’application.<\/span><\/span><\/span><\/p>\n

Cette puce montre ce que la maison de conception et ses outils peuvent r\u00e9aliser. On pense qu’il s’agit d’une conception servant de \u00abcarte de visite\u00bb pour aider l’entreprise \u00e0 passer \u00e0 l’octroi de licences de propri\u00e9t\u00e9 intellectuelle de ceurs de processeurs, soit le mod\u00e8le commercial mis au point par ARM. Cependant, dans l’interview, Santoro a d\u00e9clar\u00e9 que la d\u00e9cision devait attendre d’autres d\u00e9veloppements.<\/span><\/span><\/span><\/p>\n

Micro Magic a \u00e9t\u00e9 co-fond\u00e9e par Santoro et Lee Tavrow en 1995. Santoro avait acquis de l’exp\u00e9rience en travaillant auparavant chez Weitek, Apple Computer et Sun Microsystems et Tavrow chez Digital Equipment Corp. et Sun Microsystems. L’\u00e9quipe avait de l’exp\u00e9rience dans la conception de SRAM \u00e0 acc\u00e8s rapide et a d\u00e9velopp\u00e9 des outils de conception sp\u00e9cialis\u00e9s pour pour un layout bas\u00e9 sur la synchronisation et l’optimisation des chemins de donn\u00e9es. Cela a conduit \u00e0 l’acquisition de Micro Magic en d\u00e9cembre 2000 par Juniper Networks Inc. pour 260 millions de dollars. Les fondateurs de Micro Magic ont red\u00e9marr\u00e9 l’entreprise en 2004 et travaillent depuis dans le domaine des licences d’outils EDA et des services de conception.<\/span><\/span><\/span><\/p>\n

Lire aussi:<\/strong><\/p>\n

Linker de Segger r\u00e9duit la taille des applications RISC-V<\/a><\/p>\n

Le projet europ\u00e9en LEGaTO booste l’Edge computing de 100x <\/a><\/p>\n

Codasip lance 3 processeurs RISC\u2011V multicoeurs pour IA Edge <\/a><\/p>\n

Premier processeur IA analogique <\/a><\/p>\n

Premi\u00e8res \u00e9tapes pour NOEL-V le chip spatial europ\u00e9en multicore RISC-V <\/a><\/p>\n

Related links and articles: <\/strong><\/p>\n

www.micromagic.com<\/a><\/p>\n

www.embcc.org<\/a><\/p>\n

News articles: <\/strong><\/p>\n

CEO interview: Silicon Valley is still the place where the magic happens<\/a><\/p>\n

EDA company claims world’s fastest 64bit RISC-V core<\/a><\/p>\n

RISC-V core out-clocks Apple, SiFive; available as IP<\/a><\/p>\n

Ambiq launches Apollo4 SoC on 22ULL<\/a><\/p>\n

Minima\/ARM: Dynamic margining in near-threshold design<\/a><\/p>\n

Sub-threshold design – A revolutionary approach to eliminating power<\/a><\/p>\n","protected":false},"excerpt":{"rendered":"

Un c\u0153ur de processeur RISC-V a \u00e9t\u00e9 construit, y compris des caches de niveau un, qui ne consomme que 10 mW lorsqu’il est utilis\u00e9 dans la r\u00e9gion de seuil de tension \u00e0 350 mV.<\/p>\n","protected":false},"author":12,"featured_media":163379,"comment_status":"open","ping_status":"closed","sticky":false,"template":"","format":"standard","meta":{"_acf_changed":false,"footnotes":""},"categories":[883],"tags":[889,899,919,913,905,906,908,917],"domains":[47],"ppma_author":[1144],"class_list":["post-38558","post","type-post","status-publish","format-standard","has-post-thumbnail","hentry","category-technologies","tag-analog-fr","tag-eda-cad-tools-fr","tag-iot-fr","tag-materials-processes-fr","tag-memory-data-storage-fr","tag-mpus-mcus-fr","tag-plds-fpgas-asics-fr","tag-software-embedded-tools-fr","domains-electronique-eci"],"acf":[],"yoast_head":"Coeur de Processeur 1GHz RISC-V ne consommant que 10mW ...<\/title>\n<meta name=\"description\" content=\"Un c\u0153ur de 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