{"id":382022,"date":"2022-04-26T18:23:09","date_gmt":"2022-04-26T16:23:09","guid":{"rendered":"https:\/\/www.eenewseurope.com\/?p=382022"},"modified":"2022-04-26T18:23:09","modified_gmt":"2022-04-26T16:23:09","slug":"synopsys-lance-des-ip-de-processeurs-ia-pour-socs","status":"publish","type":"post","link":"https:\/\/www.ecinews.fr\/fr\/synopsys-lance-des-ip-de-processeurs-ia-pour-socs\/","title":{"rendered":"Synopsys lance des IP de processeurs IA pour SoCs"},"content":{"rendered":"<p><span class=\"VIiyi\" lang=\"fr\"><span class=\"JLqJ4b\" data-language-for-alternatives=\"fr\" data-language-to-translate-into=\"en\" data-phrase-index=\"0\" data-number-of-phrases=\"1\"><span class=\"Q4iAWc\">Les DesignWare ARC NPX6 et NPX6FS NPU IP r\u00e9pondent aux exigences du calcul en temps r\u00e9el avec une consommation d&rsquo;\u00e9nergie ultra-faible pour les applications d&rsquo;IA. La bo\u00eete \u00e0 outils de d\u00e9veloppement DesignWare ARC MetaWare MX fournit un environnement de compilation complet avec un partitionnement automatique de l&rsquo;algorithme de r\u00e9seau neuronal pour maximiser l&rsquo;utilisation des ressources. <\/span><\/span><\/span><\/p>\n<h4>Autres articles Synopsys <\/h4>\n<ul>\n<li class=\"title\"><a href=\"https:\/\/www.ecinews.fr\/fr\/intel-et-synopsys-en-route-vers-une-collision-frontale-sur-arc\/\" target=\"_blank\" rel=\"noopener\">Intel et Synopsys en route vers une collision frontale sur ARC ?<\/a><\/li>\n<li class=\"title\"><a href=\"https:\/\/www.ecinews.fr\/fr\/synopsys-rachete-moortec-pour-concurrencer-mentor\/\" target=\"_blank\" rel=\"noopener\">Synopsys rach\u00e8te Moortec pour concurrencer Mentor<\/a><\/li>\n<li><a href=\"https:\/\/www.eenewseurope.com\/en\/synopsys-targets-ai-cloud-with-esilicon-ip-assets-acquisition\/\">Synopsys targets AI, cloud with eSilicon IP assets<\/a><\/li>\n<li><a href=\"https:\/\/www.eenewseurope.com\/en\/synopsys-launches-arc-dsp-for-embedded-ai\/\">Synopsys launches ARC DSP for embedded AI<\/a><\/li>\n<li><a href=\"https:\/\/www.eenewseurope.com\/en\/infineon-synopsys-develop-ai-accelerator-chip-for-smart-cars\/\">Infineon, Synopsys develop AI accelerator chip for smart cars<\/a><\/li>\n<\/ul>\n<p><span class=\"VIiyi\" lang=\"fr\"><span class=\"JLqJ4b\" data-language-for-alternatives=\"fr\" data-language-to-translate-into=\"en\" data-phrase-index=\"0\" data-number-of-phrases=\"1\"><span class=\"Q4iAWc\">Les syst\u00e8mes avanc\u00e9s d&rsquo;aide \u00e0 la conduite (ADAS), la surveillance, les t\u00e9l\u00e9viseurs et cam\u00e9ras num\u00e9riques et d&rsquo;autres applications d&rsquo;intelligence artificielle \u00e9mergentes qui impl\u00e9mentent des mod\u00e8les de r\u00e9seaux neuronaux complexes sollicitent davantage les ressources de calcul et de m\u00e9moire, souvent pour des fonctions critiques pour la s\u00e9curit\u00e9. Pour r\u00e9pondre \u00e0 la gamme d&rsquo;exigences des applications, l&rsquo;IP ARC NPX6 NPU offre :<\/span><\/span><\/span><\/p>\n<ul>\n<li><span class=\"VIiyi\" lang=\"fr\"><span class=\"JLqJ4b\" data-language-for-alternatives=\"fr\" data-language-to-translate-into=\"en\" data-phrase-index=\"0\" data-number-of-phrases=\"1\"><span class=\"Q4iAWc\">\u00c9volutivit\u00e9 de 4K \u00e0 96K MACs<\/span><\/span><\/span><\/li>\n<li><span class=\"VIiyi\" lang=\"fr\"><span class=\"JLqJ4b\" data-language-for-alternatives=\"fr\" data-language-to-translate-into=\"en\" data-phrase-index=\"0\" data-number-of-phrases=\"1\"><span class=\"Q4iAWc\"> Fournit, en une seule instance, jusqu&rsquo;\u00e0 250\u00a0 t\u00e9ra op\u00e9rations par seconde (TOPS) minimum \u00e0 1,3 GHz sur des process 5 nm , ou jusqu&rsquo;\u00e0 440 TOPS en utilisant de nouvelles fonctionnalit\u00e9s de parcimonie, qui peuvent augmenter les performances et r\u00e9duire les besoins \u00e9nerg\u00e9tiques pour ex\u00e9cuter un r\u00e9seau de neurones <\/span><\/span><\/span><\/li>\n<li><span class=\"VIiyi\" lang=\"fr\"><span class=\"JLqJ4b\" data-language-for-alternatives=\"fr\" data-language-to-translate-into=\"en\" data-phrase-index=\"0\" data-number-of-phrases=\"1\"><span class=\"Q4iAWc\">Int\u00e8gre des fonctionnalit\u00e9s de connectivit\u00e9 mat\u00e9rielle et logicielle qui permettent la mise en \u0153uvre de plusieurs instances NPU pour atteindre jusqu&rsquo;\u00e0 3 500 TOPS de performances sur un seul SoC <\/span><\/span><\/span><\/li>\n<li><span class=\"VIiyi\" lang=\"fr\"><span class=\"JLqJ4b\" data-language-for-alternatives=\"fr\" data-language-to-translate-into=\"en\" data-phrase-index=\"0\" data-number-of-phrases=\"1\"><span class=\"Q4iAWc\">Fournit plus de 50 fois les performances de la configuration maximale de l&rsquo;IP du processeur ARC EV7x <\/span><\/span><\/span><\/li>\n<li><span class=\"VIiyi\" lang=\"fr\"><span class=\"JLqJ4b\" data-language-for-alternatives=\"fr\" data-language-to-translate-into=\"en\" data-phrase-index=\"0\" data-number-of-phrases=\"1\"><span class=\"Q4iAWc\">Offre une prise en charge optionnelle de la virgule flottante 16 bits \u00e0 l&rsquo;int\u00e9rieur du mat\u00e9riel de traitement neuronal, maximisant les performances de la couche et simplifiant la transition des GPU utilis\u00e9s pour le prototypage d&rsquo;IA vers des SoC produits en volume optimis\u00e9s en termes de puissance et de surface de puce.<br \/>\n<\/span><\/span><\/span><\/li>\n<\/ul>\n<p><span class=\"VIiyi\" lang=\"fr\"><span class=\"JLqJ4b\" data-language-for-alternatives=\"fr\" data-language-to-translate-into=\"en\" data-phrase-index=\"0\" data-number-of-phrases=\"1\"><span class=\"Q4iAWc\">L&rsquo;IP DesignWare ARC NPX6FS NPU r\u00e9pond aux exigences strictes de d\u00e9tection al\u00e9atoire des d\u00e9fauts mat\u00e9riels et de flux de d\u00e9veloppement de s\u00e9curit\u00e9 fonctionnelle syst\u00e9matique pour atteindre la conformit\u00e9 ISO 26262 ASIL D. Les processeurs, avec une documentation de s\u00e9curit\u00e9 compl\u00e8te incluse, disposent de m\u00e9canismes de s\u00e9curit\u00e9 d\u00e9di\u00e9s pour la conformit\u00e9 \u00e0 la norme ISO 26262 et r\u00e9pondent aux exigences de criticit\u00e9 mixte et de virtualisation des architectures zonales de nouvelle g\u00e9n\u00e9ration.<\/span><\/span><\/span><\/p>\n<p><span class=\"VIiyi\" lang=\"fr\"><span class=\"JLqJ4b\" data-language-for-alternatives=\"fr\" data-language-to-translate-into=\"en\" data-phrase-index=\"0\" data-number-of-phrases=\"1\"><span class=\"Q4iAWc\">La bo\u00eete \u00e0 outils de d\u00e9veloppement ARC MetaWare MX comprend des compilateurs et un d\u00e9bogueur, un kit de d\u00e9veloppement logiciel (SDK) de r\u00e9seau neuronal, des plates-formes virtuelles SDK, des runtimes et des biblioth\u00e8ques, ainsi que des mod\u00e8les de simulation avanc\u00e9s. MetaWare MX offre une cha\u00eene d&rsquo;outils unique pour acc\u00e9l\u00e9rer le d\u00e9veloppement d&rsquo;applications et partitionne automatiquement les algorithmes sur les ressources MAC pour un traitement hautement efficace. Pour les applications automobiles critiques pour la s\u00e9curit\u00e9, la bo\u00eete \u00e0 outils de d\u00e9veloppement MetaWare MX pour la s\u00e9curit\u00e9 comprend un manuel de s\u00e9curit\u00e9 et un guide de s\u00e9curit\u00e9 pour aider les d\u00e9veloppeurs \u00e0 r\u00e9pondre aux exigences ISO 26262 et \u00e0 se pr\u00e9parer aux tests de conformit\u00e9 ISO 26262.<\/span><\/span><\/span><\/p>\n<p><span class=\"VIiyi\" lang=\"fr\"><span class=\"JLqJ4b\" data-language-for-alternatives=\"fr\" data-language-to-translate-into=\"en\" data-phrase-index=\"0\" data-number-of-phrases=\"1\"><span class=\"Q4iAWc\">\u00ab\u00a0Des images \u00e0 plus haute r\u00e9solution, plus de cam\u00e9ras dans les syst\u00e8mes et des algorithmes plus complexes font que les exigences de traitement de l&rsquo;IA atteignent des performances TOPS \u00e9lev\u00e9es\u00a0\u00bb, d\u00e9clare John Koeter, vice-pr\u00e9sident principal, marketing et strat\u00e9gie du groupe de solutions Synopsys. \u00ab\u00a0Avec les nouveaux DesignWare ARC NPX6 et l&rsquo;IP NPX6FS NPU, ainsi que les kits d&rsquo;outils de d\u00e9veloppement MetaWare MX, les concepteurs peuvent tirer parti des derniers mod\u00e8les de r\u00e9seaux neuronaux, r\u00e9pondre aux demandes croissantes de performances et acc\u00e9l\u00e9rer la mise sur le march\u00e9 de leurs prochains SoC intelligents.\u00a0\u00bb DesignWare ARC NPX6 NPU IP, NPX6FS NPU IP et la bo\u00eete \u00e0 outils de d\u00e9veloppement MetaWare MX sont d\u00e9sormais disponibles pour les premiers clients.<\/span><\/span><\/span><\/p>\n<p><a href=\"https:\/\/www.synopsys.com\/\">Synopsys<\/a><\/p>\n<h4>Other articles on eeNews Europe\u00a0<\/h4>\n<ul>\n<li><a href=\"https:\/\/www.eenewseurope.com\/en\/learning-to-live-with-supply-chain-stress\/\">Learning to live with supply chain stress<\/a><\/li>\n<li><a href=\"https:\/\/www.eenewseurope.com\/en\/tsmc-looks-to-2nm-in-2024\/\">TSMC looks to 2nm in 2024<\/a><\/li>\n<li><a href=\"https:\/\/www.eenewseurope.com\/en\/top-ten-semiconductor-companies-in-2021\/\">Top ten semiconductor companies in 2021<\/a><\/li>\n<li><a href=\"https:\/\/www.eenewseurope.com\/en\/e1-1bn-for-a-european-photonics-supply-chain\/\">\u20ac1.1bn for a European photonics supply chain<\/a><\/li>\n<li><a href=\"https:\/\/www.eenewseurope.com\/en\/raspberry-pi-warns-of-bots-as-supply-still-tight\/\">Raspberry Pi warns of bots as supply still tight<\/a><\/li>\n<\/ul>\n<p>&nbsp;<\/p>\n","protected":false},"excerpt":{"rendered":"<p>Synopsys a lanc\u00e9 des IP de c\u0153urs d&rsquo;acc\u00e9l\u00e9rateur IA bas\u00e9s sur son architecture ARC extensible pour les conceptions de syst\u00e8mes sur puce.<\/p>\n","protected":false},"author":34,"featured_media":381208,"comment_status":"closed","ping_status":"closed","sticky":false,"template":"","format":"standard","meta":{"_acf_changed":false,"footnotes":""},"categories":[881],"tags":[890],"domains":[47],"ppma_author":[1153],"class_list":["post-382022","post","type-post","status-publish","format-standard","has-post-thumbnail","hentry","category-nouveaux-produits","tag-powermanagement-fr","domains-electronique-eci"],"acf":[],"yoast_head":"<title>Synopsys lance des IP de processeurs IA pour SoCs ...<\/title>\n<meta name=\"description\" content=\"Synopsys a lanc\u00e9 des IP de c\u0153urs d&#039;acc\u00e9l\u00e9rateur IA bas\u00e9s sur son architecture ARC extensible pour les conceptions de syst\u00e8mes sur puce.\" \/>\n<meta name=\"robots\" content=\"index, follow, max-snippet:-1, max-image-preview:large, max-video-preview:-1\" \/>\n<link rel=\"canonical\" href=\"https:\/\/www.ecinews.fr\/fr\/wp-json\/wp\/v2\/posts\/382022\/\" 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