{"id":379672,"date":"2022-04-07T19:02:40","date_gmt":"2022-04-07T17:02:40","guid":{"rendered":"https:\/\/www.eenewseurope.com\/?p=379672"},"modified":"2022-04-07T19:02:40","modified_gmt":"2022-04-07T17:02:40","slug":"lencapsulage-des-puces-devient-le-goulot-detranglement","status":"publish","type":"post","link":"https:\/\/www.ecinews.fr\/fr\/lencapsulage-des-puces-devient-le-goulot-detranglement\/","title":{"rendered":"L&rsquo;encapsulage des puces devient le goulot d&rsquo;\u00e9tranglement"},"content":{"rendered":"<p><span class=\"VIiyi\" lang=\"fr\"><span class=\"JLqJ4b\" data-language-for-alternatives=\"fr\" data-language-to-translate-into=\"en\" data-phrase-index=\"0\" data-number-of-phrases=\"1\"><span class=\"Q4iAWc\">Les entreprises de conditionnement ont \u00e9t\u00e9 durement touch\u00e9es par les annulations de commandes au d\u00e9but de la pand\u00e9mie de Covid-19 et ont d\u00fb licencier du personnel, voire fermer. Alors que la production de silicium augmente, ils ont du mal \u00e0 faire face \u00e0 l&rsquo;explosion des commandes avec la capacit\u00e9 existante, ce qui repousse les d\u00e9lais de livraison.<\/span><\/span><\/span><\/p>\n<ul>\n<li>\n<p class=\"title\"><a href=\"https:\/\/www.ecinews.fr\/fr\/flux-eda-reduisant-le-temps-de-modelisation-de-mois-a-jours\/\" target=\"_blank\" rel=\"noopener\">Flux EDA r\u00e9duisant le temps de mod\u00e9lisation de mois \u00e0 jours<\/a><\/p>\n<\/li>\n<li><a href=\"https:\/\/www.eenewseurope.com\/en\/driving-leading-edge-chip-design-from-europe\/\">Driving leading edge chip design from Europe<\/a><\/li>\n<li><u><a href=\"https:\/\/www.eenewseurope.com\/en\/sondrel-tapes-out-its-largest-chip\/\">Sondrel tapes out its largest chip<\/a><\/u><\/li>\n<li><a href=\"https:\/\/www.eenewseurope.com\/en\/sondrel-looks-for-100-engineers-as-it-ramps-5nm-designs\/\">Sondrel looks for 100 engineers as it ramps 5nm designs<\/a><\/li>\n<\/ul>\n<p><span class=\"VIiyi\" lang=\"fr\"><span class=\"JLqJ4b\" data-language-for-alternatives=\"fr\" data-language-to-translate-into=\"en\" data-phrase-index=\"0\" data-number-of-phrases=\"1\"><span class=\"Q4iAWc\">\u00ab\u00a0La s\u00e9quence de r\u00e9servation des \u00e9tapes de la cha\u00eene d&rsquo;approvisionnement a compl\u00e8tement chang\u00e9. Auparavant, une fois la plase de conception termin\u00e9e on envoyait les donn\u00e9es \u00e0 la Fab o\u00f9 la production prend encore environ 12 semaines. Dans le m\u00eame temps, les d\u00e9tails de la mise sous bo\u00eetier \u00e9taient envoy\u00e9s \u00e0 l&rsquo;entreprise d&rsquo;encapsulation afin qu&rsquo;elle soit pr\u00eate avant le silicium \u00bb, a d\u00e9clar\u00e9 Alaa Alani, responsable du packaging de Sondrel. \u00ab\u00a0Le nouveau calendrier signifie que la conception du bo\u00eetier doit \u00eatre termin\u00e9e et r\u00e9serv\u00e9e 20 semaines ou plus avant la conception finale du silicium pour garantir que le silicium et le packaging se rejoignent au bon moment.\u00a0\u00bb<\/span><\/span><\/span><\/p>\n<p><span class=\"VIiyi\" lang=\"fr\"><span class=\"JLqJ4b\" data-language-for-alternatives=\"fr\" data-language-to-translate-into=\"en\" data-phrase-index=\"0\" data-number-of-phrases=\"1\"><span class=\"Q4iAWc\">Ne pas en \u00eatre conscient et planifier en cons\u00e9quence pourrait retarder la production d&rsquo;une puce jusqu&rsquo;\u00e0 40 semaines. Sondrel propose un service complet de conception et de fabrication d&rsquo;ASIC cl\u00e9 en main et a donc identifi\u00e9 cela comme un probl\u00e8me croissant dans la cha\u00eene d&rsquo;approvisionnement. <\/span><\/span><\/span><\/p>\n<p><span class=\"VIiyi\" lang=\"fr\"><span class=\"JLqJ4b\" data-language-for-alternatives=\"fr\" data-language-to-translate-into=\"en\" data-phrase-index=\"0\" data-number-of-phrases=\"1\"><span class=\"Q4iAWc\">Une fa\u00e7on de minimiser l&rsquo;impact des retards consiste \u00e0 commencer la planification et la conception du package SoC en attribuant des \u00ab\u00a0bumps\u00a0\u00bb (contacts) et en attribuant leurs coordonn\u00e9es x\/y par rapport au coin de la puce. D\u00e9placer cette \u00e9tape beaucoup plus t\u00f4t dans la s\u00e9quence de la cha\u00eene d&rsquo;approvisionnement \u00e9vite un retard massif et co\u00fbteux.<\/span><\/span><\/span><\/p>\n<p class=\"title\"><a href=\"https:\/\/www.ecinews.fr\/fr\/tsmc-et-le-japon-se-partagent-le-cout-dune-usine-de-ci-a-tokyo\/\" target=\"_blank\" rel=\"noopener\">TSMC et le Japon se partagent le co\u00fbt d\u2019une usine de CI \u00e0 Tokyo<\/a><\/p>\n<p><span class=\"VIiyi\" lang=\"fr\"><span class=\"JLqJ4b\" data-language-for-alternatives=\"fr\" data-language-to-translate-into=\"en\" data-phrase-index=\"0\" data-number-of-phrases=\"1\"><span class=\"Q4iAWc\">Les emplacements des \u00ab\u00a0bumps\u00a0\u00bb sont d\u00e9termin\u00e9s pour chacune des macros et des PHY comme sp\u00e9cifi\u00e9 par les fournisseurs IP \u00e0 l&rsquo;aide du plan d&rsquo;implantation et des emplacements des partitions SoC. Pour les macros dures telles que PCIe, HDMI et autres, les emplacements des bumps sont sp\u00e9cifi\u00e9s par leur d\u00e9calage relatif par rapport au coin macro alors que dans les macros logicielles (par exemple, DDR), il est bas\u00e9 sur un certain mod\u00e8le et un pas minimum utilis\u00e9 dans l&rsquo;affectation des bumps.<\/span><\/span><\/span><\/p>\n<p><span class=\"VIiyi\" lang=\"fr\"><span class=\"JLqJ4b\" data-language-for-alternatives=\"fr\" data-language-to-translate-into=\"en\" data-phrase-index=\"0\" data-number-of-phrases=\"1\"><span class=\"Q4iAWc\">\u00ab\u00a0Notre r\u00e9putation repose sur l&rsquo;att\u00e9nuation des risques du projet d&rsquo;un client en garantissant la qualit\u00e9 de notre travail de conception et en gardant le doigt sur le pouls de chaque \u00e9tape de la cha\u00eene d&rsquo;approvisionnement pour identifier et r\u00e9soudre les probl\u00e8mes afin que les puces soient livr\u00e9es dans les d\u00e9lais\u00a0\u00bb, a d\u00e9clar\u00e9 Graham Curren, fondateur et PDG de Sondrel.<\/span><\/span><\/span><\/p>\n<p>&nbsp;<\/p>\n<p><iframe data-src=\"\/\/www.youtube.com\/embed\/if5No8jKNvY\" width=\"400\" height=\"224\" allowfullscreen=\"allowfullscreen\" src=\"data:image\/svg+xml;base64,PHN2ZyB3aWR0aD0iMSIgaGVpZ2h0PSIxIiB4bWxucz0iaHR0cDovL3d3dy53My5vcmcvMjAwMC9zdmciPjwvc3ZnPg==\" class=\"lazyload\" data-load-mode=\"1\"><\/iframe><\/p>\n<p><a href=\"http:\/\/www.sondrel.com\">www.sondrel.com<\/a><\/p>\n<p>Related articles<\/p>\n<ul>\n<li><u><a href=\"https:\/\/www.eenewseurope.com\/en\/sondrel-semi-custom-4tops-ai-design\/\">Sondrel semi-custom 4TOPS AI design<\/a><\/u><\/li>\n<li><u><a href=\"https:\/\/www.eenewseurope.com\/en\/sondrel-launches-quad-channel-ip-for-adas-asics\/\">Sondrel launches quad channel IP for ADAS ASICs<\/a><\/u><\/li>\n<li><a href=\"https:\/\/www.eenewsanalog.com\/en\/sondrel-agrees-to-buy-imagination-soc-design-group\/\">Sondrel agrees to buy Imagination SoC design group<\/a><\/li>\n<\/ul>\n<p>Other articles on eeNews Europe<\/p>\n<ul>\n<li><a href=\"https:\/\/www.eenewseurope.com\/en\/synopsys-boosts-chip-design-with-cloud-platform\/\">Synopsys boosts chip design with cloud platform<\/a><\/li>\n<li><a href=\"https:\/\/www.eenewseurope.com\/en\/earth-digital-twin-project-launches\/\">Earth digital twin project launches<\/a><\/li>\n<li><a href=\"https:\/\/www.eenewseurope.com\/en\/glass-processors-aim-to-boost-edge-ai\/\">Glass processors aim to boost edge AI<\/a><\/li>\n<li><a href=\"https:\/\/www.eenewseurope.com\/en\/swiss-deal-to-boost-quantum-computer-design\/\">Swiss deal to boost quantum computer design<\/a><\/li>\n<\/ul>\n","protected":false},"excerpt":{"rendered":"<p>La soci\u00e9t\u00e9 britannique de conception de puces Sondrel met en garde contre les probl\u00e8mes d&rsquo;encapsulation des puces, les d\u00e9lais passant d&rsquo;environ 8 semaines \u00e0 50 semaines ou plus.<\/p>\n","protected":false},"author":34,"featured_media":379539,"comment_status":"closed","ping_status":"closed","sticky":false,"template":"","format":"standard","meta":{"_acf_changed":false,"footnotes":""},"categories":[880],"tags":[899,913],"domains":[47],"ppma_author":[1153],"class_list":["post-379672","post","type-post","status-publish","format-standard","has-post-thumbnail","hentry","category-actualites-economiques","tag-eda-cad-tools-fr","tag-materials-processes-fr","domains-electronique-eci"],"acf":[],"yoast_head":"<title>L&#039;encapsulage des puces devient le goulot d&#039;\u00e9tranglement ...<\/title>\n<meta name=\"description\" content=\"Sondrel met en garde contre les probl\u00e8mes d&#039;encapsulation des puces, les d\u00e9lais passant d&#039;environ 8 semaines \u00e0 50 semaines ou plus.\" \/>\n<meta name=\"robots\" content=\"index, follow, max-snippet:-1, max-image-preview:large, max-video-preview:-1\" \/>\n<link rel=\"canonical\" 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