{"id":37649,"date":"2021-02-24T18:49:05","date_gmt":"2021-02-24T18:49:05","guid":{"rendered":"https:\/\/\/sipearl-fabrique-sa-puce-6nm-hpc-chez-tsmc\/"},"modified":"2021-02-24T18:49:05","modified_gmt":"2021-02-24T18:49:05","slug":"sipearl-fabrique-sa-puce-6nm-hpc-chez-tsmc","status":"publish","type":"post","link":"https:\/\/www.ecinews.fr\/fr\/sipearl-fabrique-sa-puce-6nm-hpc-chez-tsmc\/","title":{"rendered":"SiPearl fabrique sa puce 6nm HPC chez TSMC"},"content":{"rendered":"<p><!-- Global site tag (gtag.js) - Google Analytics --><\/p>\n<p>\u00a0 window.dataLayer = window.dataLayer || [];<\/p>\n<p>\u00a0 function gtag(){dataLayer.push(arguments);}<\/p>\n<p>\u00a0 gtag(&lsquo;js&rsquo;, new Date());\u00a0 gtag(&lsquo;config&rsquo;, &lsquo;UA-160857065-1&rsquo;);<\/p>\n<p><span class=\"VIiyi\" lang=\"fr\"><span class=\"JLqJ4b\" data-language-for-alternatives=\"fr\" data-language-to-translate-into=\"auto\" data-phrase-index=\"0\"><span>Le concepteur de puces fran\u00e7ais SiPearl s&rsquo;est associ\u00e9 \u00e0 Open-Silicon Research (OSR) en Inde pour d\u00e9velopper une puce ARM 6 nm pour le calcul haute performance embarqu\u00e9 (HPC) dans un bo\u00eetier 2.5D.<\/span><\/span><\/span><\/p>\n<p><span class=\"VIiyi\" lang=\"fr\"><span class=\"JLqJ4b\" data-language-for-alternatives=\"fr\" data-language-to-translate-into=\"auto\" data-phrase-index=\"0\"><span>La puce, nomm\u00e9e Rhea, sera bas\u00e9e sur 64 c\u0153urs ARM avec plus de 30 milliards de transistors et sera construite sur le process 6 nm de TSMC. Cela utilisera le programme Value Chain Aggregator (VCA) par l\u2019interm\u00e9diaire de la soci\u00e9t\u00e9 m\u00e8re am\u00e9ricaine d\u2019OSR, OpenFive, qui est la filiale open IP du d\u00e9veloppeur de puces RISC-V SiFive. SiPearl a d\u00e9j\u00e0 une licence ARM pour utiliser le noyau Neoverse V1, nom de code Zeus, et l&rsquo;utilisera pour Rhea.<\/span><\/span><\/span><\/p>\n<ul>\n<li>\n<p><a href=\"https:\/\/www.eenewseurope.com\/news\/arm-splits-its-neoverse-datacentre-server-chip-designs\">ARM SPLITS ITS NEOVERSE HPC&nbsp;CHIP DESIGNS<\/a><\/p>\n<\/li>\n<\/ul>\n<p><span class=\"VIiyi\" lang=\"fr\"><span class=\"JLqJ4b\" data-language-for-alternatives=\"fr\" data-language-to-translate-into=\"auto\" data-phrase-index=\"0\"><span>La conception du SoC utilisera \u00e9galement certains \u00e9l\u00e9ments RISC-V ainsi que le sous-syst\u00e8me IP de m\u00e9moire \u00e0 bande passante \u00e9lev\u00e9e (HBM2E) d&rsquo;OSR, l&rsquo;interconnexion die-to-die (D2D) et la puce m\u00e9moire HBM dans un seul bo\u00eetier avanc\u00e9 2.5D. Cependant, le SoC devrait \u00eatre livr\u00e9 au quatri\u00e8me trimestre 2022 etil reste donc un long chemin \u00e0 parcourir pour finaliser la conception et l&rsquo;int\u00e9gration.<\/span><\/span><\/span><\/p>\n<p><span class=\"VIiyi\" lang=\"fr\"><span class=\"JLqJ4b\" data-language-for-alternatives=\"fr\" data-language-to-translate-into=\"auto\" data-phrase-index=\"0\"><span>La collaboration pluriannuelle avec OSR \u00e9largira la gamme de conceptions HPC de Sipearl, en utilisant la mise en \u0153uvre de conception physique profond\u00e9ment submicronique d&rsquo;OSR, un bo\u00eetier 2.5D avanc\u00e9 et une gestion globale de la cha\u00eene d&rsquo;approvisionnement.<\/span><\/span><\/span><\/p>\n<p><span class=\"VIiyi\" lang=\"fr\"><span class=\"JLqJ4b\" data-language-for-alternatives=\"fr\" data-language-to-translate-into=\"auto\" data-phrase-index=\"0\"><span>Le SoC est destin\u00e9 aux applications HPC utilisant l&rsquo;intelligence artificielle (IA) telles que la conduite autonome, la reconnaissance faciale et la g\u00e9nomique qui g\u00e9n\u00e8rent tous de grandes quantit\u00e9s de donn\u00e9es.<\/span><\/span><\/span><\/p>\n<p><span class=\"VIiyi\" lang=\"fr\"><span class=\"JLqJ4b\" data-language-for-alternatives=\"fr\" data-language-to-translate-into=\"auto\" data-phrase-index=\"0\"><span>Open-Silicon Research contribuera \u00e9galement \u00e0 une m\u00e9thodologie de conception physique submicronique profonde de pointe qui permettra de mettre en \u0153uvre efficacement la puce SoC 6 nm avec une expertise avanc\u00e9e dans l&rsquo;assemblege 2.5D pour g\u00e9rer une dissipation thermique tr\u00e8s \u00e9lev\u00e9e, et l&rsquo;exp\u00e9rience de la cha\u00eene d&rsquo;approvisionnement pour assurer une mise en production en volume.<\/span><\/span><\/span><\/p>\n<p><span class=\"VIiyi\" lang=\"fr\"><span class=\"JLqJ4b\" data-language-for-alternatives=\"fr\" data-language-to-translate-into=\"auto\" data-phrase-index=\"0\"><span>\u00abNous appr\u00e9cions grandement notre partenariat avec Open-Silicon Research, et nous sommes ravis d&rsquo;utiliser l&rsquo;exp\u00e9rience de la soci\u00e9t\u00e9 dans la mise en \u0153uvre de tr\u00e8s grandes conceptions de silicium personnalis\u00e9es submicroniques profondes. OSR a \u00e9galement une grande exp\u00e9rience pour des volumes de production \u00e9lev\u00e9s et une gestion de la cha\u00eene d&rsquo;approvisionnement mondiale, qui est essentielle pour fournir cette solution SoC 6 nm tr\u00e8s complexe avec une IP HBM2E diff\u00e9renci\u00e9e dans un package 2.5D tr\u00e8s avanc\u00e9 \u00bb, a d\u00e9clar\u00e9 Philippe Notton, fondateur de SiPearl. \u00abNous sommes convaincus que ce partenariat offrira de vastes opportunit\u00e9s de d\u00e9veloppement de nouvelles applications HPC aupr\u00e8s de nos clients communs.\u00bb<\/span><\/span><\/span><\/p>\n<p><span class=\"VIiyi\" lang=\"fr\"><span class=\"JLqJ4b\" data-language-for-alternatives=\"fr\" data-language-to-translate-into=\"auto\" data-phrase-index=\"0\"><span>\u00abSiPearl est un leader mondial du HPC, et nous sommes extr\u00eamement fiers de nous associer avec eux dans le d\u00e9veloppement de cette solution SoC de nouvelle g\u00e9n\u00e9ration\u00bb, a d\u00e9clar\u00e9 Huzefa Cutlerywala, vice-pr\u00e9sident des ventes internationales et CEO d&rsquo;Open-Silicon Research en Inde. \u00abCette initiative tire parti de l&rsquo;expertise collaborative avanc\u00e9e en mati\u00e8re de silicium des deux soci\u00e9t\u00e9s et fera progresser consid\u00e9rablement l&rsquo;adoption de SoC personnalis\u00e9s dans les n\u0153uds de processus inf\u00e9rieurs \u00e0 6 nm, avec un packaging 2.5D et lib\u00e8rera les tr\u00e8s hauts d\u00e9bits de m\u00e9moire n\u00e9cessaires aux applications HPC.\u00bb<\/span><\/span><\/span><\/p>\n<p><span class=\"VIiyi\" lang=\"fr\"><span class=\"JLqJ4b\" data-language-for-alternatives=\"fr\" data-language-to-translate-into=\"auto\" data-phrase-index=\"0\"><span>SiPearl est d\u00e9j\u00e0 fortement impliqu\u00e9 dans des projets europ\u00e9ens de conception de puces HPC tels que le projet European Processor Initiative (EPI), qui con\u00e7oit le microprocesseur haute performance et basse consommation pour le supercalculateur europ\u00e9en exascale. Elle est \u00e9galement membre du consortium Mont-Blanc 2020 pour \u00e9quiper l&rsquo;Europe d&rsquo;un microprocesseur de calcul haute performance d\u00e9di\u00e9, modulaire et \u00e9conome en \u00e9nergie, et est membre du collectif PlayFrance.Digital.<\/span><\/span><\/span><\/p>\n<p><a href=\"http:\/\/www.sipearl.com\">www.sipearl.com<\/a>; <a href=\"http:\/\/www.openfive.com\">www.openfive.com<\/a><\/p>\n<h3>Related SiPearl articles&nbsp;<\/h3>\n<ul>\n<li><a href=\"https:\/\/www.eenewseurope.com\/news\/sipearl-joins-european-hpc-group\">FRENCH HPC CHIP DESIGNER JOINS EUROPEAN HPC GROUP<\/a><\/li>\n<li><a href=\"https:\/\/www.eenewseurope.com\/news\/european-exascale-supercomputer-chip-project-updates-its-roadmap\">EUROPEAN EXASCALE SUPERCOMPUTER CHIP PROJECT UPDATES ITS ROADMAP<\/a><\/li>\n<li><a href=\"https:\/\/www.eenewsanalog.com\/news\/european-processor-startup-joins-cxl-consortium\">EUROPEAN PROCESSOR STARTUP JOINS CXL CONSORTIUM<\/a><\/li>\n<\/ul>\n<p><strong>Other articles on eeNews Europe&nbsp;<\/strong><\/p>\n<ul>\n<li><a href=\"https:\/\/www.eenewseurope.com\/news\/nxp-infineon-plants-hit-power-outage-texas-storm\">NXP, Infineon plants hit by power outage in Texas storm<\/a><\/li>\n<li><a href=\"https:\/\/www.eenewseurope.com\/news\/italvolt-gigafactory\">BritishVolt gigafactory founder tries again in Italy<\/a><\/li>\n<li><a href=\"https:\/\/www.eenewseurope.com\/news\/europe-needs-wake-its-30-year-semiconductor-sleep\">Europe needs to wake from its 30-year semiconductor sleep<\/a><\/li>\n<li><a href=\"https:\/\/www.eenewseurope.com\/news\/fd-soi-breakthrough-ABB\">FD-SOI breakthrough boosts performance<\/a><\/li>\n<li><a href=\"https:\/\/www.eenewseurope.com\/news\/bosch-blockchain-trial-secure-aiot\">Bosch in blockchain trial for secure AIoT<\/a><\/li>\n<\/ul>\n","protected":false},"excerpt":{"rendered":"<p>Le SoC syst\u00e8me sur puce de calcul haute performance (HPC) bas\u00e9 sur ARM, appel\u00e9 Rhea, con\u00e7u par SiPearl en France, sera fabriqu\u00e9 en 6 nm par TSMC<\/p>\n","protected":false},"author":12,"featured_media":160601,"comment_status":"open","ping_status":"closed","sticky":false,"template":"","format":"standard","meta":{"_acf_changed":false,"footnotes":""},"categories":[883],"tags":[920,906],"domains":[47],"ppma_author":[1144],"class_list":["post-37649","post","type-post","status-publish","format-standard","has-post-thumbnail","hentry","category-technologies","tag-artificialintelligence-fr","tag-mpus-mcus-fr","domains-electronique-eci"],"acf":[],"yoast_head":"<title>SiPearl fabrique sa puce 6nm HPC chez TSMC ...<\/title>\n<meta name=\"description\" content=\"Le SoC syst\u00e8me sur puce de calcul haute performance (HPC) bas\u00e9 sur ARM, appel\u00e9 Rhea, con\u00e7u par SiPearl en France, sera fabriqu\u00e9 en 6 nm par TSMC\" \/>\n<meta name=\"robots\" content=\"index, follow, max-snippet:-1, max-image-preview:large, max-video-preview:-1\" \/>\n<link rel=\"canonical\" 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