{"id":234472,"date":"2015-10-12T22:00:00","date_gmt":"2015-10-12T22:00:00","guid":{"rendered":"https:\/\/eenewseurope.artwhere.co\/cadence-et-limec-annoncent-la-realisation-complete-du-premier-circuit-integre-de-test-en-geometrie-de-5-nm\/"},"modified":"2015-10-12T22:00:00","modified_gmt":"2015-10-12T22:00:00","slug":"cadence-et-limec-annoncent-la-realisation-complete-du-premier-circuit-integre-de-test-en-geometrie-de-5-nm","status":"publish","type":"post","link":"https:\/\/www.ecinews.fr\/fr\/cadence-et-limec-annoncent-la-realisation-complete-du-premier-circuit-integre-de-test-en-geometrie-de-5-nm\/","title":{"rendered":"Cadence et l\u2019IMEC annoncent la r\u00e9alisation compl\u00e8te du premier circuit int\u00e9gr\u00e9 de test en g\u00e9om\u00e9trie de 5 nm"},"content":{"rendered":"

Pour produire ce circuit de test, l’IMEC et Cadence ont optimisé des règles de conception, des bibliothèques et une technologie de placement-routage en vue d’obtenir des valeurs de Puissance, Performances et Surface (PPA) optimales à l’aide de la plateforme Innovus Implementation System de Cadence. Utilisant un design de processeur, ils ont réalisé avec succès le "tape out" d’une série de conceptions en lithographie extrême ultra-violet (EUV), ainsi qu’avec la technologie SAQP (Self-Aligned Quadruple Patterning) pour la photolithographie 193i, où les pas métalliques ont été réduits de 32 nm (nominal) à 24 nm afin de repousser les limites pour la création des motifs (patterning).
\nLa plateforme Innovus Implementation System est une solution d’implémentation physique de dernière génération qui donne aux développeurs de systèmes sur puce électronique (SoC) la possibilité de réaliser leurs projets en bénéficiant de valeurs PPA optimales, tout en réduisant les délais de mise sur le marché. Associant une architecture massivement parallèle à des technologies d’optimisation révolutionnaires, cette plateforme améliore typiquement les valeurs PPA de 10 à 20 % tout en multipliant la capacité et la vitesse d’exécution du flot complet jusqu’à un facteur 10.<\/p>\n<\/p>\n

www.cadence.com\/news\/innovus<\/a><\/p>\n","protected":false},"excerpt":{"rendered":"

Le centre de recherche en nano\u00e9lectronique IMEC et Cadence Design Systems annoncent le premier \u00abtape out\u00bb d\u2019un circuit int\u00e9gr\u00e9 de test r\u00e9alis\u00e9 en g\u00e9om\u00e9trie de 5 nm utilisant les technologies de lithographie extr\u00eame ultra-violet (EUV) et de photolithographie 193 nm \u00e0 immersion (193i).<\/p>\n","protected":false},"author":22,"featured_media":234473,"comment_status":"closed","ping_status":"closed","sticky":false,"template":"","format":"standard","meta":{"_acf_changed":false,"footnotes":""},"categories":[],"tags":[],"domains":[47],"ppma_author":[1149],"class_list":["post-234472","post","type-post","status-publish","format-standard","has-post-thumbnail","hentry","domains-electronique-eci"],"acf":[],"yoast_head":"Cadence et l\u2019IMEC annoncent la r\u00e9alisation compl\u00e8te du prem...<\/title>\n<meta name=\"description\" content=\"Le centre de recherche en nano\u00e9lectronique IMEC et Cadence Design Systems annoncent le premier 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