{"id":229254,"date":"2014-02-23T23:00:00","date_gmt":"2014-02-23T23:00:00","guid":{"rendered":"https:\/\/eenewseurope.artwhere.co\/design-de-reference-dinitialisation-securisee-base-fpga-pour-systemes-embarques\/"},"modified":"2014-02-23T23:00:00","modified_gmt":"2014-02-23T23:00:00","slug":"design-de-reference-dinitialisation-securisee-base-fpga-pour-systemes-embarques","status":"publish","type":"post","link":"https:\/\/www.ecinews.fr\/fr\/design-de-reference-dinitialisation-securisee-base-fpga-pour-systemes-embarques\/","title":{"rendered":"Design de r\u00e9f\u00e9rence d\u2019initialisation s\u00e9curis\u00e9e bas\u00e9 FPGA pour syst\u00e8mes embarqu\u00e9s"},"content":{"rendered":"<p>Sans initialisation s&eacute;curis&eacute;e, tout code ex&eacute;cut&eacute; sur un syst&egrave;me embarqu&eacute; est, par d&eacute;finition, non fiable. Les syst&egrave;mes non fiables repr&eacute;sentent un risque pour les marques, exposent les entreprises &agrave; des responsabilit&eacute;s et peuvent parfois causer des pertes humaines. Ce design de r&eacute;f&eacute;rence impl&eacute;mente une &quot;cha&icirc;ne de confiance&quot;. A chaque &eacute;tape d&rsquo;initialisation allant jusqu&rsquo;au niveau sup&eacute;rieur applicatif, chaque phase est valid&eacute;e par le code pr&eacute;c&eacute;demment authentifi&eacute; avant qu&rsquo;il ne soit permis de poursuivre l&rsquo;ex&eacute;cution du code.<br \/>\nCe design de r&eacute;f&eacute;rence s&rsquo;appuie sur le SoC FPGA SmartFusion2 propri&eacute;taire dont les fonctions de s&eacute;curit&eacute; avanc&eacute;es incluent le stockage des cl&eacute;s, un g&eacute;n&eacute;rateur de nombres al&eacute;atoires non d&eacute;terministe, le stockage du code d&rsquo;initialisation en flash embarqu&eacute;e s&eacute;curis&eacute;e (eNVM) et une &eacute;mulation temps r&eacute;el de flash &agrave; interface SPI permettant l&rsquo;initialisation s&eacute;curis&eacute;e d&rsquo;un processeur externe &agrave; vitesse r&eacute;elle. Ces dispositifs affichent une plus grande s&eacute;curit&eacute; de conception que d&rsquo;autres FPGA, et incluent des mesures de protection contre les intrusions par analyse diff&eacute;rentielle de consommation (DPA), via une technologie sous licence CRI.<br \/>\nLa conception de r&eacute;f&eacute;rence fournit aussi une version publique du produit de s&eacute;curit&eacute; WhiteboxCRYPTO de la soci&eacute;t&eacute; qui transporte une cl&eacute; de chiffrage sym&eacute;trique sous forme purement textuelle &agrave; travers une d&eacute;composition alg&eacute;brique complexe et une forte &quot;obfuscation&quot;. Une interface utilisateur graphique (GUI) permet aux utilisateurs de chiffrer leur code applicatif en vue d&rsquo;une programmation en flash SPI et d&rsquo;un d&eacute;chiffrage dans le processeur h&ocirc;te. De plus, un guide tr&egrave;s complet assiste les d&eacute;veloppeurs pour l&rsquo;impl&eacute;mentation de l&rsquo;initialisation s&eacute;curis&eacute;e dans leurs syst&egrave;mes embarqu&eacute;s.<br \/>\n&quot;Nous continuons &agrave; &eacute;tendre notre offre S&eacute;curit&eacute; et &agrave; relever les d&eacute;fis de plus en plus difficiles de la s&eacute;curit&eacute; des syst&egrave;mes informatiques,&quot; d&eacute;clare Tim Morin, directeur de marketing chez Microsemi. &quot;Tr&egrave;s peu de processeurs disposent aujourd&rsquo;hui d&rsquo;une initialisation s&eacute;curis&eacute;e et sont dignes de confiance, alors que les menaces n&rsquo;ont jamais &eacute;t&eacute; aussi fortes, des processeurs &eacute;tant embarqu&eacute;s dans des applications de plus en plus critiques, comme l&rsquo;aide &agrave; la conduite dans l&rsquo;automobile, le contr&ocirc;le de processus et l&rsquo;automatisation de la fabrication, et notre monde &eacute;mergent hyper connect&eacute; de l&rsquo;internet des objets. Notre design novateur prot&egrave;ge ces syst&egrave;mes et applications au niveau le plus basique, r&eacute;duisant le risque utilisateur et assurant que tous les processeurs ex&eacute;cutent un code authentifi&eacute;.&quot;<br \/>\nCette conception de r&eacute;f&eacute;rence bas&eacute;e FPGA SmartFusion2 peut &eacute;galement &ecirc;tre accompagn&eacute;e des designs de r&eacute;f&eacute;rence pour initialisation s&eacute;curis&eacute;s de processeurs d&rsquo;application de fabricants comme ARM, Intel et Freescale. <\/p>\n<\/p>\n<p><a title=\"www.microsemi.com\/products\/fpga-soc\/security\/secure-boot\" target=\"_blank\" href=\"http:\/\/www.microsemi.com\/products\/fpga-soc\/security\/secure-boot\" rel=\"noopener\">www.microsemi.com\/products\/fpga-soc\/security\/secure-boot<\/a><\/p>\n","protected":false},"excerpt":{"rendered":"<p>Le design de r\u00e9f\u00e9rence d\u2019initialisation s\u00e9curis\u00e9e de Microsemi exploite les fonctions de s\u00e9curit\u00e9 avanc\u00e9es de ses SoC FPGA SmartFusion2 pour initialiser, en toute s\u00e9curit\u00e9, tout processeur d\u2019application au sein du syst\u00e8me embarqu\u00e9 et assurer que le code qui s\u2019ex\u00e9cute est fiable. Les applications s\u2019ex\u00e9cutant sur ce processeur \u00e9tendent cette confiance \u00e0 tout leur syst\u00e8me et ceux associ\u00e9s. <\/p>\n","protected":false},"author":22,"featured_media":229255,"comment_status":"closed","ping_status":"closed","sticky":false,"template":"","format":"standard","meta":{"_acf_changed":false,"footnotes":""},"categories":[881],"tags":[],"domains":[47],"ppma_author":[1149],"class_list":["post-229254","post","type-post","status-publish","format-standard","has-post-thumbnail","hentry","category-nouveaux-produits","domains-electronique-eci"],"acf":[],"yoast_head":"<title>Design de r\u00e9f\u00e9rence d\u2019initialisation s\u00e9curis\u00e9e bas\u00e9 FPGA...<\/title>\n<meta name=\"description\" content=\"Le design de r\u00e9f\u00e9rence d\u2019initialisation s\u00e9curis\u00e9e de Microsemi exploite les fonctions de s\u00e9curit\u00e9 avanc\u00e9es de ses SoC FPGA SmartFusion2 pour...\" \/>\n<meta name=\"robots\" content=\"index, follow, max-snippet:-1, max-image-preview:large, max-video-preview:-1\" \/>\n<link rel=\"canonical\" href=\"https:\/\/www.ecinews.fr\/fr\/wp-json\/wp\/v2\/posts\/229254\/\" \/>\n<meta property=\"og:locale\" content=\"fr_FR\" \/>\n<meta property=\"og:type\" content=\"article\" \/>\n<meta property=\"og:title\" content=\"Design de r\u00e9f\u00e9rence d\u2019initialisation s\u00e9curis\u00e9e bas\u00e9 FPGA pour syst\u00e8mes embarqu\u00e9s\" \/>\n<meta property=\"og:description\" content=\"Le design de r\u00e9f\u00e9rence d\u2019initialisation s\u00e9curis\u00e9e de Microsemi exploite les fonctions de s\u00e9curit\u00e9 avanc\u00e9es de ses SoC FPGA SmartFusion2 pour initialiser, en toute s\u00e9curit\u00e9, tout processeur d\u2019application au sein du syst\u00e8me embarqu\u00e9 et assurer que le code qui s\u2019ex\u00e9cute est fiable. Les applications s\u2019ex\u00e9cutant sur ce processeur \u00e9tendent cette confiance \u00e0 tout leur syst\u00e8me et ceux associ\u00e9s.\" \/>\n<meta property=\"og:url\" content=\"https:\/\/www.ecinews.fr\/fr\/wp-json\/wp\/v2\/posts\/229254\/\" \/>\n<meta property=\"og:site_name\" content=\"EENewsEurope\" \/>\n<meta property=\"article:published_time\" content=\"2014-02-23T23:00:00+00:00\" \/>\n<meta property=\"og:image\" content=\"https:\/\/www.ecinews.fr\/wp-content\/uploads\/import\/default\/files\/import\/eci6780_microsemi_snag-0024.jpg\" \/>\n\t<meta property=\"og:image:width\" content=\"897\" \/>\n\t<meta property=\"og:image:height\" content=\"497\" \/>\n\t<meta property=\"og:image:type\" content=\"image\/jpeg\" \/>\n<meta name=\"author\" content=\"eeNews Europe\" \/>\n<meta name=\"twitter:card\" content=\"summary_large_image\" \/>\n<meta name=\"twitter:label1\" content=\"Written by\" \/>\n\t<meta name=\"twitter:data1\" content=\"eeNews Europe\" \/>\n\t<meta name=\"twitter:label2\" content=\"Est. reading time\" \/>\n\t<meta name=\"twitter:data2\" content=\"3 minutes\" \/>\n<script type=\"application\/ld+json\" class=\"yoast-schema-graph\">{\"@context\":\"https:\/\/schema.org\",\"@graph\":[{\"@type\":\"Article\",\"@id\":\"https:\/\/www.ecinews.fr\/fr\/design-de-reference-dinitialisation-securisee-base-fpga-pour-systemes-embarques\/#article\",\"isPartOf\":{\"@id\":\"https:\/\/www.ecinews.fr\/fr\/design-de-reference-dinitialisation-securisee-base-fpga-pour-systemes-embarques\/\"},\"author\":{\"name\":\"eeNews Europe\",\"@id\":\"https:\/\/www.eenewseurope.com\/en\/#\/schema\/person\/9eff4051fa9dac8230052de45e32b0f4\"},\"headline\":\"Design de r\u00e9f\u00e9rence d\u2019initialisation s\u00e9curis\u00e9e bas\u00e9 FPGA pour syst\u00e8mes embarqu\u00e9s\",\"datePublished\":\"2014-02-23T23:00:00+00:00\",\"dateModified\":\"2014-02-23T23:00:00+00:00\",\"mainEntityOfPage\":{\"@id\":\"https:\/\/www.ecinews.fr\/fr\/design-de-reference-dinitialisation-securisee-base-fpga-pour-systemes-embarques\/\"},\"wordCount\":638,\"publisher\":{\"@id\":\"https:\/\/www.eenewseurope.com\/en\/#organization\"},\"articleSection\":[\"Nouveaux produits\"],\"inLanguage\":\"fr-FR\"},{\"@type\":\"WebPage\",\"@id\":\"https:\/\/www.ecinews.fr\/fr\/design-de-reference-dinitialisation-securisee-base-fpga-pour-systemes-embarques\/\",\"url\":\"https:\/\/www.ecinews.fr\/fr\/design-de-reference-dinitialisation-securisee-base-fpga-pour-systemes-embarques\/\",\"name\":\"Design de r\u00e9f\u00e9rence d\u2019initialisation s\u00e9curis\u00e9e bas\u00e9 FPGA pour syst\u00e8mes embarqu\u00e9s -\",\"isPartOf\":{\"@id\":\"https:\/\/www.eenewseurope.com\/en\/#website\"},\"datePublished\":\"2014-02-23T23:00:00+00:00\",\"dateModified\":\"2014-02-23T23:00:00+00:00\",\"breadcrumb\":{\"@id\":\"https:\/\/www.ecinews.fr\/fr\/design-de-reference-dinitialisation-securisee-base-fpga-pour-systemes-embarques\/#breadcrumb\"},\"inLanguage\":\"fr-FR\",\"potentialAction\":[{\"@type\":\"ReadAction\",\"target\":[\"https:\/\/www.ecinews.fr\/fr\/design-de-reference-dinitialisation-securisee-base-fpga-pour-systemes-embarques\/\"]}]},{\"@type\":\"BreadcrumbList\",\"@id\":\"https:\/\/www.ecinews.fr\/fr\/design-de-reference-dinitialisation-securisee-base-fpga-pour-systemes-embarques\/#breadcrumb\",\"itemListElement\":[{\"@type\":\"ListItem\",\"position\":1,\"name\":\"Home\",\"item\":\"https:\/\/cdn.eenewseurope.com\/fr\/\"},{\"@type\":\"ListItem\",\"position\":2,\"name\":\"Design de r\u00e9f\u00e9rence d\u2019initialisation s\u00e9curis\u00e9e bas\u00e9 FPGA pour syst\u00e8mes embarqu\u00e9s\"}]},{\"@type\":\"WebSite\",\"@id\":\"https:\/\/www.eenewseurope.com\/en\/#website\",\"url\":\"https:\/\/www.eenewseurope.com\/en\/\",\"name\":\"EENewsEurope\",\"description\":\"Just another WordPress site\",\"publisher\":{\"@id\":\"https:\/\/www.eenewseurope.com\/en\/#organization\"},\"potentialAction\":[{\"@type\":\"SearchAction\",\"target\":{\"@type\":\"EntryPoint\",\"urlTemplate\":\"https:\/\/www.eenewseurope.com\/en\/?s={search_term_string}\"},\"query-input\":\"required name=search_term_string\"}],\"inLanguage\":\"fr-FR\"},{\"@type\":\"Organization\",\"@id\":\"https:\/\/www.eenewseurope.com\/en\/#organization\",\"name\":\"EENewsEurope\",\"url\":\"https:\/\/www.eenewseurope.com\/en\/\",\"logo\":{\"@type\":\"ImageObject\",\"inLanguage\":\"fr-FR\",\"@id\":\"https:\/\/www.eenewseurope.com\/en\/#\/schema\/logo\/image\/\",\"url\":\"https:\/\/www.ecinews.fr\/wp-content\/uploads\/2022\/02\/logo-1.jpg\",\"contentUrl\":\"https:\/\/www.ecinews.fr\/wp-content\/uploads\/2022\/02\/logo-1.jpg\",\"width\":283,\"height\":113,\"caption\":\"EENewsEurope\"},\"image\":{\"@id\":\"https:\/\/www.eenewseurope.com\/en\/#\/schema\/logo\/image\/\"}},{\"@type\":\"Person\",\"@id\":\"https:\/\/www.eenewseurope.com\/en\/#\/schema\/person\/9eff4051fa9dac8230052de45e32b0f4\",\"name\":\"eeNews Europe\",\"image\":{\"@type\":\"ImageObject\",\"inLanguage\":\"fr-FR\",\"@id\":\"https:\/\/www.eenewseurope.com\/en\/#\/schema\/person\/image\/fae8f0cb15861c4ae0ed4872e2c9fc22\",\"url\":\"https:\/\/secure.gravatar.com\/avatar\/5081509054e28b04ecd976976e723ce0?s=96&d=mm&r=g\",\"contentUrl\":\"https:\/\/secure.gravatar.com\/avatar\/5081509054e28b04ecd976976e723ce0?s=96&d=mm&r=g\",\"caption\":\"eeNews Europe\"}}]}<\/script>","yoast_head_json":{"title":"Design de r\u00e9f\u00e9rence d\u2019initialisation s\u00e9curis\u00e9e bas\u00e9 FPGA...","description":"Le design de r\u00e9f\u00e9rence d\u2019initialisation s\u00e9curis\u00e9e de Microsemi exploite les fonctions de s\u00e9curit\u00e9 avanc\u00e9es de ses SoC FPGA SmartFusion2 pour...","robots":{"index":"index","follow":"follow","max-snippet":"max-snippet:-1","max-image-preview":"max-image-preview:large","max-video-preview":"max-video-preview:-1"},"canonical":"https:\/\/www.ecinews.fr\/fr\/wp-json\/wp\/v2\/posts\/229254\/","og_locale":"fr_FR","og_type":"article","og_title":"Design de r\u00e9f\u00e9rence d\u2019initialisation s\u00e9curis\u00e9e bas\u00e9 FPGA pour syst\u00e8mes embarqu\u00e9s","og_description":"Le design de r\u00e9f\u00e9rence d\u2019initialisation s\u00e9curis\u00e9e de Microsemi exploite les fonctions de s\u00e9curit\u00e9 avanc\u00e9es de ses SoC FPGA SmartFusion2 pour initialiser, en toute s\u00e9curit\u00e9, tout processeur d\u2019application au sein du syst\u00e8me embarqu\u00e9 et assurer que le code qui s\u2019ex\u00e9cute est fiable. Les applications s\u2019ex\u00e9cutant sur ce processeur \u00e9tendent cette confiance \u00e0 tout leur syst\u00e8me et ceux associ\u00e9s.","og_url":"https:\/\/www.ecinews.fr\/fr\/wp-json\/wp\/v2\/posts\/229254\/","og_site_name":"EENewsEurope","article_published_time":"2014-02-23T23:00:00+00:00","og_image":[{"width":897,"height":497,"url":"https:\/\/www.ecinews.fr\/wp-content\/uploads\/import\/default\/files\/import\/eci6780_microsemi_snag-0024.jpg","type":"image\/jpeg"}],"author":"eeNews Europe","twitter_card":"summary_large_image","twitter_misc":{"Written by":"eeNews Europe","Est. reading time":"3 minutes"},"schema":{"@context":"https:\/\/schema.org","@graph":[{"@type":"Article","@id":"https:\/\/www.ecinews.fr\/fr\/design-de-reference-dinitialisation-securisee-base-fpga-pour-systemes-embarques\/#article","isPartOf":{"@id":"https:\/\/www.ecinews.fr\/fr\/design-de-reference-dinitialisation-securisee-base-fpga-pour-systemes-embarques\/"},"author":{"name":"eeNews Europe","@id":"https:\/\/www.eenewseurope.com\/en\/#\/schema\/person\/9eff4051fa9dac8230052de45e32b0f4"},"headline":"Design de r\u00e9f\u00e9rence d\u2019initialisation s\u00e9curis\u00e9e bas\u00e9 FPGA pour syst\u00e8mes embarqu\u00e9s","datePublished":"2014-02-23T23:00:00+00:00","dateModified":"2014-02-23T23:00:00+00:00","mainEntityOfPage":{"@id":"https:\/\/www.ecinews.fr\/fr\/design-de-reference-dinitialisation-securisee-base-fpga-pour-systemes-embarques\/"},"wordCount":638,"publisher":{"@id":"https:\/\/www.eenewseurope.com\/en\/#organization"},"articleSection":["Nouveaux produits"],"inLanguage":"fr-FR"},{"@type":"WebPage","@id":"https:\/\/www.ecinews.fr\/fr\/design-de-reference-dinitialisation-securisee-base-fpga-pour-systemes-embarques\/","url":"https:\/\/www.ecinews.fr\/fr\/design-de-reference-dinitialisation-securisee-base-fpga-pour-systemes-embarques\/","name":"Design de r\u00e9f\u00e9rence d\u2019initialisation s\u00e9curis\u00e9e bas\u00e9 FPGA pour syst\u00e8mes embarqu\u00e9s -","isPartOf":{"@id":"https:\/\/www.eenewseurope.com\/en\/#website"},"datePublished":"2014-02-23T23:00:00+00:00","dateModified":"2014-02-23T23:00:00+00:00","breadcrumb":{"@id":"https:\/\/www.ecinews.fr\/fr\/design-de-reference-dinitialisation-securisee-base-fpga-pour-systemes-embarques\/#breadcrumb"},"inLanguage":"fr-FR","potentialAction":[{"@type":"ReadAction","target":["https:\/\/www.ecinews.fr\/fr\/design-de-reference-dinitialisation-securisee-base-fpga-pour-systemes-embarques\/"]}]},{"@type":"BreadcrumbList","@id":"https:\/\/www.ecinews.fr\/fr\/design-de-reference-dinitialisation-securisee-base-fpga-pour-systemes-embarques\/#breadcrumb","itemListElement":[{"@type":"ListItem","position":1,"name":"Home","item":"https:\/\/cdn.eenewseurope.com\/fr\/"},{"@type":"ListItem","position":2,"name":"Design de r\u00e9f\u00e9rence d\u2019initialisation s\u00e9curis\u00e9e bas\u00e9 FPGA pour syst\u00e8mes embarqu\u00e9s"}]},{"@type":"WebSite","@id":"https:\/\/www.eenewseurope.com\/en\/#website","url":"https:\/\/www.eenewseurope.com\/en\/","name":"EENewsEurope","description":"Just another WordPress site","publisher":{"@id":"https:\/\/www.eenewseurope.com\/en\/#organization"},"potentialAction":[{"@type":"SearchAction","target":{"@type":"EntryPoint","urlTemplate":"https:\/\/www.eenewseurope.com\/en\/?s={search_term_string}"},"query-input":"required name=search_term_string"}],"inLanguage":"fr-FR"},{"@type":"Organization","@id":"https:\/\/www.eenewseurope.com\/en\/#organization","name":"EENewsEurope","url":"https:\/\/www.eenewseurope.com\/en\/","logo":{"@type":"ImageObject","inLanguage":"fr-FR","@id":"https:\/\/www.eenewseurope.com\/en\/#\/schema\/logo\/image\/","url":"https:\/\/www.ecinews.fr\/wp-content\/uploads\/2022\/02\/logo-1.jpg","contentUrl":"https:\/\/www.ecinews.fr\/wp-content\/uploads\/2022\/02\/logo-1.jpg","width":283,"height":113,"caption":"EENewsEurope"},"image":{"@id":"https:\/\/www.eenewseurope.com\/en\/#\/schema\/logo\/image\/"}},{"@type":"Person","@id":"https:\/\/www.eenewseurope.com\/en\/#\/schema\/person\/9eff4051fa9dac8230052de45e32b0f4","name":"eeNews Europe","image":{"@type":"ImageObject","inLanguage":"fr-FR","@id":"https:\/\/www.eenewseurope.com\/en\/#\/schema\/person\/image\/fae8f0cb15861c4ae0ed4872e2c9fc22","url":"https:\/\/secure.gravatar.com\/avatar\/5081509054e28b04ecd976976e723ce0?s=96&d=mm&r=g","contentUrl":"https:\/\/secure.gravatar.com\/avatar\/5081509054e28b04ecd976976e723ce0?s=96&d=mm&r=g","caption":"eeNews Europe"}}]}},"authors":[{"term_id":1149,"user_id":22,"is_guest":0,"slug":"eenews-europe","display_name":"eeNews Europe","avatar_url":"https:\/\/secure.gravatar.com\/avatar\/5081509054e28b04ecd976976e723ce0?s=96&d=mm&r=g","0":null,"1":"","2":"","3":"","4":"","5":"","6":"","7":"","8":""}],"_links":{"self":[{"href":"https:\/\/www.ecinews.fr\/fr\/wp-json\/wp\/v2\/posts\/229254"}],"collection":[{"href":"https:\/\/www.ecinews.fr\/fr\/wp-json\/wp\/v2\/posts"}],"about":[{"href":"https:\/\/www.ecinews.fr\/fr\/wp-json\/wp\/v2\/types\/post"}],"author":[{"embeddable":true,"href":"https:\/\/www.ecinews.fr\/fr\/wp-json\/wp\/v2\/users\/22"}],"replies":[{"embeddable":true,"href":"https:\/\/www.ecinews.fr\/fr\/wp-json\/wp\/v2\/comments?post=229254"}],"version-history":[{"count":0,"href":"https:\/\/www.ecinews.fr\/fr\/wp-json\/wp\/v2\/posts\/229254\/revisions"}],"wp:featuredmedia":[{"embeddable":true,"href":"https:\/\/www.ecinews.fr\/fr\/wp-json\/wp\/v2\/media\/229255"}],"wp:attachment":[{"href":"https:\/\/www.ecinews.fr\/fr\/wp-json\/wp\/v2\/media?parent=229254"}],"wp:term":[{"taxonomy":"category","embeddable":true,"href":"https:\/\/www.ecinews.fr\/fr\/wp-json\/wp\/v2\/categories?post=229254"},{"taxonomy":"post_tag","embeddable":true,"href":"https:\/\/www.ecinews.fr\/fr\/wp-json\/wp\/v2\/tags?post=229254"},{"taxonomy":"domains","embeddable":true,"href":"https:\/\/www.ecinews.fr\/fr\/wp-json\/wp\/v2\/domains?post=229254"},{"taxonomy":"author","embeddable":true,"href":"https:\/\/www.ecinews.fr\/fr\/wp-json\/wp\/v2\/ppma_author?post=229254"}],"curies":[{"name":"wp","href":"https:\/\/api.w.org\/{rel}","templated":true}]}}