{"id":224633,"date":"2012-06-26T22:00:00","date_gmt":"2012-06-26T22:00:00","guid":{"rendered":"https:\/\/eenewseurope.artwhere.co\/gains-en-performances-et-productivite-pour-les-concepteurs-systemes\/"},"modified":"2012-06-26T22:00:00","modified_gmt":"2012-06-26T22:00:00","slug":"gains-en-performances-et-productivite-pour-les-concepteurs-systemes","status":"publish","type":"post","link":"https:\/\/www.ecinews.fr\/fr\/gains-en-performances-et-productivite-pour-les-concepteurs-systemes\/","title":{"rendered":"Gains en performances et productivit\u00e9 pour les concepteurs syst\u00e8mes."},"content":{"rendered":"<p style=\"margin:0cm;margin-bottom:.0001pt;line-height:115%\">Avec cette version logicielle, les utilisateurs de FPGA Stratix V b&eacute;n&eacute;ficieront d&rsquo;une r&eacute;duction des temps de compilation d&rsquo;environ 35% en moyenne, tandis que les utilisateurs de FPGA Cyclone et Arria V verront diminuer les temps de compilation de 25% en moyenne par rapport &agrave; l&rsquo;&eacute;dition pr&eacute;c&eacute;dente de l&rsquo;environnement. Elle offre un support &eacute;largi pour les FPGA 28-nm et, notamment, le support initial des FPGA SoC propri&eacute;taires qui int&egrave;grent un processeur mat&eacute;riel ARM Cortex-A9 &agrave; double c&oelig;ur. Les utilisateurs ont le choix parmi une vaste gamme de FPGA 28-nm &agrave; bas co&ucirc;t, de milieu de gamme et de haut de gamme sur lesquels ils peuvent baser leurs conceptions.<br \/>\nL&rsquo;outil d&rsquo;int&eacute;gration syst&egrave;me Qsys s&rsquo;est &eacute;galement &eacute;toff&eacute; avec le support de l&rsquo;interface ARM AMBA AXI-3. Gr&acirc;ce &agrave; cette fonctionnalit&eacute;, les concepteurs peuvent interconnecter des c&oelig;urs IP et des sous-syst&egrave;mes IP faisant usage d&rsquo;interfaces standardis&eacute;es diff&eacute;rentes. Qsys est un outil d&rsquo;int&eacute;gration syst&egrave;me qui repose sur une technologie de r&eacute;seau sur puce NoC (Network-on-a-Chip) et qui fournit de ce fait une technologie d&rsquo;interconnexion &agrave; hautes performances. L&rsquo;outil simplifie le d&eacute;veloppement syst&egrave;me via l&rsquo;int&eacute;gration de fonctions IP et de sous-syst&egrave;mes IP selon une approche hi&eacute;rarchique. Les caract&eacute;ristiques conviviales apport&eacute;es &agrave; la derni&egrave;re version fournissent aux concepteurs syst&egrave;mes des fonctions automatis&eacute;es additionnelles et simplifient la r&eacute;utilisation des conceptions.<br \/>\nL&rsquo;outil DSP Builder&nbsp;v12.0 peut communiquer avec les m&eacute;moires DDR de Matlab via la console syst&egrave;me et dispose de nouvelles fonctions &agrave; virgule flottante pour une productivit&eacute; am&eacute;lior&eacute;e et une meilleure efficacit&eacute; des traitements DSP.<br \/>\nLe d&eacute;veloppement d&rsquo;applications de traitement vid&eacute;o est simplifi&eacute; gr&acirc;ce &agrave; l&rsquo;int&eacute;gration d&rsquo;un algorithme de d&eacute;tection de contours auto-adaptatif dans&nbsp; la fonction Scaler II MegaCore et gr&acirc;ce &agrave; de nouveaux c&oelig;urs IP Video Monitor et Trace System pour l&rsquo;interface de streaming Avalon-Streaming (Avalon-ST).<\/p>\n<p style=\"margin:0cm;margin-bottom:.0001pt;line-height:115%\">&quot;De la planification jusqu&rsquo;aux phases de compilation et d&rsquo;impl&eacute;mentation, l&rsquo;environnement Quartus II d&rsquo;Altera simplifie l&rsquo;ensemble du processus de conception&quot;, commente Vince Hu, vice-pr&eacute;sident marketing produit et corporate chez Altera. &quot;Avec la version 12.0, les utilisateurs b&eacute;n&eacute;ficient de temps de compilation acc&eacute;l&eacute;r&eacute;s et d&rsquo;un support de composants &eacute;tendu&nbsp;; ils peuvent ainsi r&eacute;pondre aux besoins en performances et aux gains de productivit&eacute; qu&rsquo;exigent les conceptions syst&egrave;mes d&rsquo;aujourd&rsquo;hui, et tout particuli&egrave;rement les projets r&eacute;alis&eacute;s en technologie 28-nm.&quot;\n<\/p>\n<p style=\"margin:0cm;margin-bottom:.0001pt;line-height:115%\">&nbsp;<\/p>\n<p><a href=\"http:\/\/www.altera.com\/q2whatsnew\" target=\"_blank\" title=\"www.altera.com\/q2whatsnew\" rel=\"noopener\">www.altera.com\/q2whatsnew<\/a><\/p>\n","protected":false},"excerpt":{"rendered":"<p>Altera lance la version V12.0 de son logiciel Quartus II qui acc\u00e9l\u00e8re les temps de compilation jusqu\u2019\u00e0 quatre fois sur les conceptions des FPGA 28-nm \u00e0 hautes performances. Cette version apporte \u00e9galement un support \u00e9largi d\u2019\u00e9volutions \u00e0 l\u2019outil d\u2019int\u00e9gration syst\u00e8me Qsys et \u00e0 l\u2019outil DSP Builder ainsi qu\u2019une offre \u00e9toff\u00e9e de c\u0153urs de propri\u00e9t\u00e9 intellectuelle.<\/p>\n","protected":false},"author":22,"featured_media":224634,"comment_status":"closed","ping_status":"closed","sticky":false,"template":"","format":"standard","meta":{"_acf_changed":false,"footnotes":""},"categories":[881],"tags":[908],"domains":[47],"ppma_author":[1149],"class_list":["post-224633","post","type-post","status-publish","format-standard","has-post-thumbnail","hentry","category-nouveaux-produits","tag-plds-fpgas-asics-fr","domains-electronique-eci"],"acf":[],"yoast_head":"<title>Gains en performances et productivit\u00e9 pour les concepteurs sys...<\/title>\n<meta name=\"description\" content=\"Altera lance la version V12.0 de son logiciel Quartus II qui acc\u00e9l\u00e8re les temps de compilation jusqu\u2019\u00e0 quatre fois sur les conceptions des FPGA 28-nm \u00e0...\" \/>\n<meta name=\"robots\" content=\"index, follow, max-snippet:-1, max-image-preview:large, max-video-preview:-1\" \/>\n<link rel=\"canonical\" href=\"https:\/\/www.ecinews.fr\/fr\/wp-json\/wp\/v2\/posts\/224633\/\" \/>\n<meta property=\"og:locale\" content=\"fr_FR\" \/>\n<meta property=\"og:type\" content=\"article\" \/>\n<meta property=\"og:title\" content=\"Gains en performances et productivit\u00e9 pour les concepteurs syst\u00e8mes.\" \/>\n<meta property=\"og:description\" content=\"Altera lance la version V12.0 de son logiciel Quartus II qui acc\u00e9l\u00e8re les temps de compilation jusqu\u2019\u00e0 quatre fois sur les conceptions des FPGA 28-nm \u00e0 hautes performances. Cette version apporte \u00e9galement un support \u00e9largi d\u2019\u00e9volutions \u00e0 l\u2019outil d\u2019int\u00e9gration syst\u00e8me Qsys et \u00e0 l\u2019outil DSP Builder ainsi qu\u2019une offre \u00e9toff\u00e9e de c\u0153urs de propri\u00e9t\u00e9 intellectuelle.\" \/>\n<meta property=\"og:url\" content=\"https:\/\/www.ecinews.fr\/fr\/wp-json\/wp\/v2\/posts\/224633\/\" \/>\n<meta property=\"og:site_name\" content=\"EENewsEurope\" \/>\n<meta property=\"article:published_time\" content=\"2012-06-26T22:00:00+00:00\" \/>\n<meta property=\"og:image\" content=\"https:\/\/www.ecinews.fr\/wp-content\/uploads\/import\/default\/files\/import\/eci6155_logo-qii-lo.jpg\" \/>\n\t<meta property=\"og:image:width\" content=\"131\" \/>\n\t<meta property=\"og:image:height\" content=\"126\" \/>\n\t<meta property=\"og:image:type\" content=\"image\/jpeg\" \/>\n<meta name=\"author\" content=\"eeNews Europe\" \/>\n<meta name=\"twitter:card\" content=\"summary_large_image\" \/>\n<meta name=\"twitter:label1\" content=\"Written by\" \/>\n\t<meta name=\"twitter:data1\" content=\"eeNews Europe\" \/>\n\t<meta name=\"twitter:label2\" content=\"Est. reading time\" \/>\n\t<meta name=\"twitter:data2\" content=\"3 minutes\" \/>\n<script type=\"application\/ld+json\" class=\"yoast-schema-graph\">{\"@context\":\"https:\/\/schema.org\",\"@graph\":[{\"@type\":\"Article\",\"@id\":\"https:\/\/www.ecinews.fr\/fr\/gains-en-performances-et-productivite-pour-les-concepteurs-systemes\/#article\",\"isPartOf\":{\"@id\":\"https:\/\/www.ecinews.fr\/fr\/gains-en-performances-et-productivite-pour-les-concepteurs-systemes\/\"},\"author\":{\"name\":\"eeNews Europe\",\"@id\":\"https:\/\/www.eenewseurope.com\/en\/#\/schema\/person\/9eff4051fa9dac8230052de45e32b0f4\"},\"headline\":\"Gains en performances et productivit\u00e9 pour les concepteurs syst\u00e8mes.\",\"datePublished\":\"2012-06-26T22:00:00+00:00\",\"dateModified\":\"2012-06-26T22:00:00+00:00\",\"mainEntityOfPage\":{\"@id\":\"https:\/\/www.ecinews.fr\/fr\/gains-en-performances-et-productivite-pour-les-concepteurs-systemes\/\"},\"wordCount\":555,\"publisher\":{\"@id\":\"https:\/\/www.eenewseurope.com\/en\/#organization\"},\"keywords\":[\"PLDs\/FPGAs\/ASICs\"],\"articleSection\":[\"Nouveaux produits\"],\"inLanguage\":\"fr-FR\"},{\"@type\":\"WebPage\",\"@id\":\"https:\/\/www.ecinews.fr\/fr\/gains-en-performances-et-productivite-pour-les-concepteurs-systemes\/\",\"url\":\"https:\/\/www.ecinews.fr\/fr\/gains-en-performances-et-productivite-pour-les-concepteurs-systemes\/\",\"name\":\"Gains en performances et productivit\u00e9 pour les concepteurs syst\u00e8mes. -\",\"isPartOf\":{\"@id\":\"https:\/\/www.eenewseurope.com\/en\/#website\"},\"datePublished\":\"2012-06-26T22:00:00+00:00\",\"dateModified\":\"2012-06-26T22:00:00+00:00\",\"breadcrumb\":{\"@id\":\"https:\/\/www.ecinews.fr\/fr\/gains-en-performances-et-productivite-pour-les-concepteurs-systemes\/#breadcrumb\"},\"inLanguage\":\"fr-FR\",\"potentialAction\":[{\"@type\":\"ReadAction\",\"target\":[\"https:\/\/www.ecinews.fr\/fr\/gains-en-performances-et-productivite-pour-les-concepteurs-systemes\/\"]}]},{\"@type\":\"BreadcrumbList\",\"@id\":\"https:\/\/www.ecinews.fr\/fr\/gains-en-performances-et-productivite-pour-les-concepteurs-systemes\/#breadcrumb\",\"itemListElement\":[{\"@type\":\"ListItem\",\"position\":1,\"name\":\"Home\",\"item\":\"https:\/\/test.ecinews.fr\/fr\/\"},{\"@type\":\"ListItem\",\"position\":2,\"name\":\"Gains en performances et productivit\u00e9 pour les concepteurs syst\u00e8mes.\"}]},{\"@type\":\"WebSite\",\"@id\":\"https:\/\/www.eenewseurope.com\/en\/#website\",\"url\":\"https:\/\/www.eenewseurope.com\/en\/\",\"name\":\"EENewsEurope\",\"description\":\"Just another WordPress site\",\"publisher\":{\"@id\":\"https:\/\/www.eenewseurope.com\/en\/#organization\"},\"potentialAction\":[{\"@type\":\"SearchAction\",\"target\":{\"@type\":\"EntryPoint\",\"urlTemplate\":\"https:\/\/www.eenewseurope.com\/en\/?s={search_term_string}\"},\"query-input\":\"required name=search_term_string\"}],\"inLanguage\":\"fr-FR\"},{\"@type\":\"Organization\",\"@id\":\"https:\/\/www.eenewseurope.com\/en\/#organization\",\"name\":\"EENewsEurope\",\"url\":\"https:\/\/www.eenewseurope.com\/en\/\",\"logo\":{\"@type\":\"ImageObject\",\"inLanguage\":\"fr-FR\",\"@id\":\"https:\/\/www.eenewseurope.com\/en\/#\/schema\/logo\/image\/\",\"url\":\"https:\/\/www.ecinews.fr\/wp-content\/uploads\/2022\/02\/logo-1.jpg\",\"contentUrl\":\"https:\/\/www.ecinews.fr\/wp-content\/uploads\/2022\/02\/logo-1.jpg\",\"width\":283,\"height\":113,\"caption\":\"EENewsEurope\"},\"image\":{\"@id\":\"https:\/\/www.eenewseurope.com\/en\/#\/schema\/logo\/image\/\"}},{\"@type\":\"Person\",\"@id\":\"https:\/\/www.eenewseurope.com\/en\/#\/schema\/person\/9eff4051fa9dac8230052de45e32b0f4\",\"name\":\"eeNews Europe\",\"image\":{\"@type\":\"ImageObject\",\"inLanguage\":\"fr-FR\",\"@id\":\"https:\/\/www.eenewseurope.com\/en\/#\/schema\/person\/image\/fae8f0cb15861c4ae0ed4872e2c9fc22\",\"url\":\"https:\/\/secure.gravatar.com\/avatar\/5081509054e28b04ecd976976e723ce0?s=96&d=mm&r=g\",\"contentUrl\":\"https:\/\/secure.gravatar.com\/avatar\/5081509054e28b04ecd976976e723ce0?s=96&d=mm&r=g\",\"caption\":\"eeNews Europe\"}}]}<\/script>","yoast_head_json":{"title":"Gains en performances et productivit\u00e9 pour les concepteurs sys...","description":"Altera lance la version V12.0 de son logiciel Quartus II qui acc\u00e9l\u00e8re les temps de compilation jusqu\u2019\u00e0 quatre fois sur les conceptions des FPGA 28-nm \u00e0...","robots":{"index":"index","follow":"follow","max-snippet":"max-snippet:-1","max-image-preview":"max-image-preview:large","max-video-preview":"max-video-preview:-1"},"canonical":"https:\/\/www.ecinews.fr\/fr\/wp-json\/wp\/v2\/posts\/224633\/","og_locale":"fr_FR","og_type":"article","og_title":"Gains en performances et productivit\u00e9 pour les concepteurs syst\u00e8mes.","og_description":"Altera lance la version V12.0 de son logiciel Quartus II qui acc\u00e9l\u00e8re les temps de compilation jusqu\u2019\u00e0 quatre fois sur les conceptions des FPGA 28-nm \u00e0 hautes performances. Cette version apporte \u00e9galement un support \u00e9largi d\u2019\u00e9volutions \u00e0 l\u2019outil d\u2019int\u00e9gration syst\u00e8me Qsys et \u00e0 l\u2019outil DSP Builder ainsi qu\u2019une offre \u00e9toff\u00e9e de c\u0153urs de propri\u00e9t\u00e9 intellectuelle.","og_url":"https:\/\/www.ecinews.fr\/fr\/wp-json\/wp\/v2\/posts\/224633\/","og_site_name":"EENewsEurope","article_published_time":"2012-06-26T22:00:00+00:00","og_image":[{"width":131,"height":126,"url":"https:\/\/www.ecinews.fr\/wp-content\/uploads\/import\/default\/files\/import\/eci6155_logo-qii-lo.jpg","type":"image\/jpeg"}],"author":"eeNews Europe","twitter_card":"summary_large_image","twitter_misc":{"Written by":"eeNews Europe","Est. reading time":"3 minutes"},"schema":{"@context":"https:\/\/schema.org","@graph":[{"@type":"Article","@id":"https:\/\/www.ecinews.fr\/fr\/gains-en-performances-et-productivite-pour-les-concepteurs-systemes\/#article","isPartOf":{"@id":"https:\/\/www.ecinews.fr\/fr\/gains-en-performances-et-productivite-pour-les-concepteurs-systemes\/"},"author":{"name":"eeNews Europe","@id":"https:\/\/www.eenewseurope.com\/en\/#\/schema\/person\/9eff4051fa9dac8230052de45e32b0f4"},"headline":"Gains en performances et productivit\u00e9 pour les concepteurs syst\u00e8mes.","datePublished":"2012-06-26T22:00:00+00:00","dateModified":"2012-06-26T22:00:00+00:00","mainEntityOfPage":{"@id":"https:\/\/www.ecinews.fr\/fr\/gains-en-performances-et-productivite-pour-les-concepteurs-systemes\/"},"wordCount":555,"publisher":{"@id":"https:\/\/www.eenewseurope.com\/en\/#organization"},"keywords":["PLDs\/FPGAs\/ASICs"],"articleSection":["Nouveaux produits"],"inLanguage":"fr-FR"},{"@type":"WebPage","@id":"https:\/\/www.ecinews.fr\/fr\/gains-en-performances-et-productivite-pour-les-concepteurs-systemes\/","url":"https:\/\/www.ecinews.fr\/fr\/gains-en-performances-et-productivite-pour-les-concepteurs-systemes\/","name":"Gains en performances et productivit\u00e9 pour les concepteurs syst\u00e8mes. -","isPartOf":{"@id":"https:\/\/www.eenewseurope.com\/en\/#website"},"datePublished":"2012-06-26T22:00:00+00:00","dateModified":"2012-06-26T22:00:00+00:00","breadcrumb":{"@id":"https:\/\/www.ecinews.fr\/fr\/gains-en-performances-et-productivite-pour-les-concepteurs-systemes\/#breadcrumb"},"inLanguage":"fr-FR","potentialAction":[{"@type":"ReadAction","target":["https:\/\/www.ecinews.fr\/fr\/gains-en-performances-et-productivite-pour-les-concepteurs-systemes\/"]}]},{"@type":"BreadcrumbList","@id":"https:\/\/www.ecinews.fr\/fr\/gains-en-performances-et-productivite-pour-les-concepteurs-systemes\/#breadcrumb","itemListElement":[{"@type":"ListItem","position":1,"name":"Home","item":"https:\/\/test.ecinews.fr\/fr\/"},{"@type":"ListItem","position":2,"name":"Gains en performances et productivit\u00e9 pour les concepteurs syst\u00e8mes."}]},{"@type":"WebSite","@id":"https:\/\/www.eenewseurope.com\/en\/#website","url":"https:\/\/www.eenewseurope.com\/en\/","name":"EENewsEurope","description":"Just another WordPress site","publisher":{"@id":"https:\/\/www.eenewseurope.com\/en\/#organization"},"potentialAction":[{"@type":"SearchAction","target":{"@type":"EntryPoint","urlTemplate":"https:\/\/www.eenewseurope.com\/en\/?s={search_term_string}"},"query-input":"required name=search_term_string"}],"inLanguage":"fr-FR"},{"@type":"Organization","@id":"https:\/\/www.eenewseurope.com\/en\/#organization","name":"EENewsEurope","url":"https:\/\/www.eenewseurope.com\/en\/","logo":{"@type":"ImageObject","inLanguage":"fr-FR","@id":"https:\/\/www.eenewseurope.com\/en\/#\/schema\/logo\/image\/","url":"https:\/\/www.ecinews.fr\/wp-content\/uploads\/2022\/02\/logo-1.jpg","contentUrl":"https:\/\/www.ecinews.fr\/wp-content\/uploads\/2022\/02\/logo-1.jpg","width":283,"height":113,"caption":"EENewsEurope"},"image":{"@id":"https:\/\/www.eenewseurope.com\/en\/#\/schema\/logo\/image\/"}},{"@type":"Person","@id":"https:\/\/www.eenewseurope.com\/en\/#\/schema\/person\/9eff4051fa9dac8230052de45e32b0f4","name":"eeNews Europe","image":{"@type":"ImageObject","inLanguage":"fr-FR","@id":"https:\/\/www.eenewseurope.com\/en\/#\/schema\/person\/image\/fae8f0cb15861c4ae0ed4872e2c9fc22","url":"https:\/\/secure.gravatar.com\/avatar\/5081509054e28b04ecd976976e723ce0?s=96&d=mm&r=g","contentUrl":"https:\/\/secure.gravatar.com\/avatar\/5081509054e28b04ecd976976e723ce0?s=96&d=mm&r=g","caption":"eeNews Europe"}}]}},"authors":[{"term_id":1149,"user_id":22,"is_guest":0,"slug":"eenews-europe","display_name":"eeNews Europe","avatar_url":"https:\/\/secure.gravatar.com\/avatar\/5081509054e28b04ecd976976e723ce0?s=96&d=mm&r=g","0":null,"1":"","2":"","3":"","4":"","5":"","6":"","7":"","8":""}],"_links":{"self":[{"href":"https:\/\/www.ecinews.fr\/fr\/wp-json\/wp\/v2\/posts\/224633"}],"collection":[{"href":"https:\/\/www.ecinews.fr\/fr\/wp-json\/wp\/v2\/posts"}],"about":[{"href":"https:\/\/www.ecinews.fr\/fr\/wp-json\/wp\/v2\/types\/post"}],"author":[{"embeddable":true,"href":"https:\/\/www.ecinews.fr\/fr\/wp-json\/wp\/v2\/users\/22"}],"replies":[{"embeddable":true,"href":"https:\/\/www.ecinews.fr\/fr\/wp-json\/wp\/v2\/comments?post=224633"}],"version-history":[{"count":0,"href":"https:\/\/www.ecinews.fr\/fr\/wp-json\/wp\/v2\/posts\/224633\/revisions"}],"wp:featuredmedia":[{"embeddable":true,"href":"https:\/\/www.ecinews.fr\/fr\/wp-json\/wp\/v2\/media\/224634"}],"wp:attachment":[{"href":"https:\/\/www.ecinews.fr\/fr\/wp-json\/wp\/v2\/media?parent=224633"}],"wp:term":[{"taxonomy":"category","embeddable":true,"href":"https:\/\/www.ecinews.fr\/fr\/wp-json\/wp\/v2\/categories?post=224633"},{"taxonomy":"post_tag","embeddable":true,"href":"https:\/\/www.ecinews.fr\/fr\/wp-json\/wp\/v2\/tags?post=224633"},{"taxonomy":"domains","embeddable":true,"href":"https:\/\/www.ecinews.fr\/fr\/wp-json\/wp\/v2\/domains?post=224633"},{"taxonomy":"author","embeddable":true,"href":"https:\/\/www.ecinews.fr\/fr\/wp-json\/wp\/v2\/ppma_author?post=224633"}],"curies":[{"name":"wp","href":"https:\/\/api.w.org\/{rel}","templated":true}]}}