{"id":175899,"date":"2017-04-14T01:00:00","date_gmt":"2017-04-14T01:00:00","guid":{"rendered":"https:\/\/eenewseurope.artwhere.co\/logiciel-de-conception-de-fpga-ameliore\/"},"modified":"2017-04-14T01:00:00","modified_gmt":"2017-04-14T01:00:00","slug":"logiciel-de-conception-de-fpga-ameliore","status":"publish","type":"post","link":"https:\/\/www.ecinews.fr\/fr\/logiciel-de-conception-de-fpga-ameliore\/","title":{"rendered":"Logiciel de conception de FPGA am\u00e9lior\u00e9"},"content":{"rendered":"<p>La suite d&rsquo;outils Libero SoC comprend le simulateur ModelSim de Mentor Graphics qui assure la v\u00e9rification ligne par ligne du code HDL. La simulation peut \u00eatre effectu\u00e9e \u00e0 tous les niveaux, comportemental (pr\u00e9-synth\u00e8se), structurel (post-synth\u00e8se) et dynamique avec r\u00e9tro-annotations. Intuitive et conviviale, l\u2019interface utilisateur graphique autorise une identification rapide des probl\u00e8mes de d\u00e9bogage. La version v11.8 comprend d\u00e9sormais ModelSim Microsemi Pro qui donne aux concepteurs la possibilit\u00e9 d\u2019acc\u00e9der \u00e0 la simulation dans des environnements en langage mixte ainsi qu&rsquo;\u00e0 une am\u00e9lioration des temps d&rsquo;ex\u00e9cution de 20% pour les versions r\u00e9centes de l&rsquo;outil.<\/p>\n<p>\u00ab\u00a0Notre Libero SoC v11.8 offre des am\u00e9liorations significatives comme ModelSim ME Pro qui supporte la simulation en langage mixte pour VHDL (VHSIC Hardware Description Language), Verilog et SystemVerilog. Cela permet aux utilisateurs de cibler un large \u00e9ventail de mod\u00e8les de propri\u00e9t\u00e9 intellectuelle (IP) sans se soucier de m\u00e9langer des langages,\u00a0\u00bb d\u00e9clare Jim Davis, vice-pr\u00e9sident de l&rsquo;ing\u00e9nierie logicielle chez Microsemi. \u00ab\u00a0Il comprend \u00e9galement les derni\u00e8res am\u00e9liorations de SmartDebug, telles que les FPGA Hardware Breakpoint (FHB), une fonctionnalit\u00e9 unique \u00e0 nos FPGA. Les FHB permettent aux utilisateurs de d\u00e9finir des points d&rsquo;arr\u00eat dans leurs conceptions et de progresser pas \u00e0 pas par cycle d&rsquo;horloge, offrant une excellente visibilit\u00e9 et r\u00e9duisant significativement le temps de d\u00e9bogage.\u00a0\u00bb<\/p>\n<p>Alors que les points d&rsquo;arr\u00eat sont employ\u00e9s traditionnellement dans les logiciels embarqu\u00e9s, ils peuvent maintenant \u00eatre utilis\u00e9s pour supporter les fonctions de d\u00e9bogage logique des FPGA. C\u2019est un moyen efficace d\u2019augmenter la productivit\u00e9, la facilit\u00e9 d&rsquo;utilisation et l&rsquo;efficacit\u00e9 des conceptions sur FPGA, car il se traduit par un temps de mise sur le march\u00e9 plus rapide, en particulier dans la phase de validation qui constitue la plus longue partie du cycle de d\u00e9veloppement de produits. Ces am\u00e9liorations significatives de SmartDebug compl\u00e8tent les fonctionnalit\u00e9s de d\u00e9bogage existantes, offrant une approche innovante pour d\u00e9boguer l&rsquo;\u00e9tat des composants \u00e0 FPGA, la m\u00e9moire et les transceivers SerDes, sans utiliser un analyseur logique int\u00e9gr\u00e9 (ILA).<\/p>\n<hr \/>\n<p>Ce logiciel v11.8 est bien adapt\u00e9 pour les conceptions FPGA visant les applications dans les secteurs de l&rsquo;a\u00e9rospatiale, de la d\u00e9fense, de la s\u00e9curit\u00e9, des communications, des centres de donn\u00e9es, de l&rsquo;industrie et de l&rsquo;automobile. Il s\u2019est dot\u00e9 de multiples fonctionnalit\u00e9s suppl\u00e9mentaires, y compris une pr\u00e9sentation de netlist offrant une visibilit\u00e9 sur diff\u00e9rentes structures internes, de nouvelles fonctions de gestion des contraintes proposant des flux de blocs et d&rsquo;entr\u00e9e\/sortie (E\/S), des am\u00e9liorations de 20% des temps d&rsquo;ex\u00e9cution de son interface utilisateur SmartTime et le support du syst\u00e8me d&rsquo;exploitation Windows 10.<\/p>\n<p>En mati\u00e8re de s\u00e9curit\u00e9, cette version propose la solution propri\u00e9taire Secured Production Programming Solution (SPPS) qui g\u00e9n\u00e8re et ins\u00e8re des cl\u00e9s cryptographiques et des flux de donn\u00e9es de configuration pour \u00e9viter la sur-fabrication, le clonage, l&rsquo;ing\u00e9nierie invers\u00e9, l&rsquo;insertion de logiciels malveillants et d&rsquo;autres menaces de s\u00e9curit\u00e9.<\/p>\n<p>Afin de faciliter une large adoption, cette version est \u00e9galement livr\u00e9e avec une licence d&rsquo;\u00e9valuation de 60 jours pour les conceptions de r\u00e9f\u00e9rence FPGA et SoC propri\u00e9taires bas\u00e9s sur de la m\u00e9moire flash, les tutoriels et les notes d&rsquo;application. Cette licence d&rsquo;\u00e9valuation conviviale et intuitive offre aux utilisateurs une m\u00e9thode plus simple pour commencer avec Libero SoC.<\/p>\n<p><a href=\"https:\/\/www.microsemi.com\/products\/fpga-soc\/design-resources\/design-software\/libero-soc\" target=\"_blank\" rel=\"noopener\">www.microsemi.com\/libero-soc<\/a><\/p>\n<p><a href=\"https:\/\/www.microsemi.com\/products\/fpga-soc\/fpgas\" target=\"_blank\" rel=\"noopener\">www.microsemi.com\/fpga-soc<\/a><\/p>\n","protected":false},"excerpt":{"rendered":"<p>R\u00e9unissant une gamme compl\u00e8te d&rsquo;outils de conception de FPGA, la version 11.8 du logiciel Libero SoC (system-on-chip) de Microsemi comprend des am\u00e9liorations significatives telles que la simulation en langage mixte, de meilleures capacit\u00e9s de d\u00e9bogage et une pr\u00e9sentation revisit\u00e9e de la netlist. En outre, elle est accompagn\u00e9e d\u2019une licence d&rsquo;\u00e9valuation pour tester les FPGA et SoC propri\u00e9taires bas\u00e9s Flash.<\/p>\n","protected":false},"author":9,"featured_media":175900,"comment_status":"closed","ping_status":"closed","sticky":false,"template":"","format":"standard","meta":{"_acf_changed":false,"footnotes":""},"categories":[881],"tags":[917],"domains":[47],"ppma_author":[1141],"class_list":["post-175899","post","type-post","status-publish","format-standard","has-post-thumbnail","hentry","category-nouveaux-produits","tag-software-embedded-tools-fr","domains-electronique-eci"],"acf":[],"yoast_head":"<title>Logiciel de conception de FPGA am\u00e9lior\u00e9 ...<\/title>\n<meta name=\"description\" content=\"R\u00e9unissant une gamme compl\u00e8te d&#039;outils de conception de FPGA, la version 11.8 du logiciel Libero SoC (system-on-chip) de Microsemi comprend des...\" \/>\n<meta name=\"robots\" content=\"index, follow, max-snippet:-1, max-image-preview:large, max-video-preview:-1\" \/>\n<link rel=\"canonical\" href=\"https:\/\/www.ecinews.fr\/fr\/wp-json\/wp\/v2\/posts\/175899\/\" \/>\n<meta property=\"og:locale\" content=\"fr_FR\" \/>\n<meta property=\"og:type\" content=\"article\" \/>\n<meta property=\"og:title\" content=\"Logiciel de conception de FPGA am\u00e9lior\u00e9\" \/>\n<meta property=\"og:description\" content=\"R\u00e9unissant une gamme compl\u00e8te d&#039;outils de conception de FPGA, la version 11.8 du logiciel Libero SoC (system-on-chip) de Microsemi comprend des am\u00e9liorations significatives telles que la simulation en langage mixte, de meilleures capacit\u00e9s de d\u00e9bogage et une pr\u00e9sentation revisit\u00e9e de la netlist. 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