{"id":157189,"date":"2021-12-09T11:30:06","date_gmt":"2021-12-09T11:30:06","guid":{"rendered":"https:\/\/eenewseurope.artwhere.co\/radioverse-chip-looks-to-drive-fpgas-out-of-5g-radios\/"},"modified":"2021-12-09T11:30:06","modified_gmt":"2021-12-09T11:30:06","slug":"radioverse-chip-looks-to-drive-fpgas-out-of-5g-radios","status":"publish","type":"post","link":"https:\/\/www.ecinews.fr\/fr\/radioverse-chip-looks-to-drive-fpgas-out-of-5g-radios\/","title":{"rendered":"RadioVerse chip looks to drive FPGAs out of 5G radios"},"content":{"rendered":"

Analog Devices is aiming to cut FPGAs out of 5G radio design with its latest software-defined system-on-chip.<\/p>\n

The RadioVerse SoC provides zero-IF RF signal processing with expanded digital functionality and RF capacity that improves 5G RU performance and energy efficiency.<\/font><\/p>\n

The ADRV9040 is the first in the new RadioVerse SoC series and offers eight transmit and receive channels of 400MHz bandwidth across a tunable range from 650 MHz to 6GHz. The 13W chip integrates carrier digital up-converters (CDUC), carrier digital down-converters (CDDC), crest factor reduction (CFR) and digital pre-distortion (DPD). This expanded signal processing can eliminate the need for a field-programmable gate array (FPGA) says ADI, reducing thermal footprint, and total system size, weight, power, and cost.<\/p>\n

The DPD algorithms in the chip were developed using advanced machine learning techniques and are optimised in close collaboration with major power amplifier (PA) vendors to ease the design burden and deliver best-in-class wide bandwidth performance. The algorithms are fully tested and validated across 4G and 5G use cases, including various PA technology types such as gallium nitride (GaN). In addition, the ZiF radio architecture simplifies RF filtering and signal chain components, reducing RU cost and development time for band and power variants designs.<\/p>\n

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