{"id":127916,"date":"2018-03-08T16:13:56","date_gmt":"2018-03-08T16:13:56","guid":{"rendered":"https:\/\/\/premiers-chips-de-test-3nm-par-imec-et-cadence\/"},"modified":"2018-03-08T16:13:56","modified_gmt":"2018-03-08T16:13:56","slug":"premiers-chips-de-test-3nm-par-imec-et-cadence","status":"publish","type":"post","link":"https:\/\/www.ecinews.fr\/fr\/premiers-chips-de-test-3nm-par-imec-et-cadence\/","title":{"rendered":"Premiers chips de test 3nm par IMEC et Cadence"},"content":{"rendered":"<p><span id=\"result_box\" lang=\"fr\"><span title=\"The 3nm node will have minimum drawn geometries lines and spaces of about 10nm and indeed the full pitch for routing on the design is 21nm giving a half pitch of 10.5nm.\">La technologie 3 nm aura des lignes de g\u00e9om\u00e9tries minimales et des \u00e9cartements d&rsquo;environ 10 nm et&nbsp; le pas total pour le routage de la conception est de 21 nm donnant un demi-pas de 10,5 nm. <\/span><span title=\"The chip is intended to be made using both extreme ultraviolet and 193 immersion lithography technology and the design rules at various levels in the chip reflect this, the two parties said.\n\n\">La puce est destin\u00e9e \u00e0 \u00eatre fabriqu\u00e9e en utilisant \u00e0 la fois la technologie de lithographie par ultraviolet extr\u00eame et par immersion 193, et les r\u00e8gles de conception des diff\u00e9rents niveaux dans la puce refl\u00e8tent cela, ont d\u00e9clar\u00e9 les deux parties.<\/span><\/span><\/p>\n<p><span id=\"result_box\" lang=\"fr\"><span title=\"IMEC utilized a common industry 64-bit CPU for the design with a custom 3nm standard cell library.\n\n\">IMEC a utilis\u00e9 un processeur 64 bits industriel courant pour la conception avec une biblioth\u00e8que de cellules standard 3nm personnalis\u00e9e.<\/span><br \/>\n<span title=\"Cadence tools used included the Innovus implementation system that makes use of massively parallel computation to for the physical implementation system to achieve power, performance and area (PPA) targets.\">Les outils de cadence utilis\u00e9s comprenaient le syst\u00e8me de mise en \u0153uvre Innovus qui utilise le calcul massivement parall\u00e8le pour que le syst\u00e8me de mise en \u0153uvre physique atteigne les objectifs de puissance, de performance et de zone (PPA). <\/span><span title=\"The Genus synthesis tool provides RTL synthesis that addresses FinFET process node requirements.\n\n\">L&rsquo;outil de synth\u00e8se Genus fournit une synth\u00e8se RTL qui r\u00e9pond aux besoins des n\u0153uds de processus FinFET.<\/span><\/span><\/p>\n<p><span id=\"result_box\" lang=\"fr\"><span title=\"For the project, EUV and 193i lithography rules were tested to provide the required resolution, while providing PPA comparison under two different patterning assumptions.\n\n\">Pour le projet, les r\u00e8gles de lithographie EUV et 193i ont \u00e9t\u00e9 test\u00e9es pour fournir la r\u00e9solution requise, tout en fournissant une comparaison de PPA selon deux hypoth\u00e8ses de cr\u00e9ation de structures diff\u00e9rentes.<\/span><\/span><\/p>\n<hr \/>\n<p><span id=\"result_box\" lang=\"fr\"><span title=\"&quot;As process dimensions reduce to the 3nm node, interconnect variation becomes much more significant,&quot; said An Steegen, executive vice president for semiconductor technology and systems at IMEC, in a statement.\">\u00ab\u00a0Alors que les dimensions du process se r\u00e9duisent au n\u0153ud de 3nm, la variatbilit\u00e9 d&rsquo;interconnexion devient beaucoup plus importante\u00a0\u00bb, a d\u00e9clar\u00e9 An Steegen, vice-pr\u00e9sident ex\u00e9cutif de la technologie et des syst\u00e8mes semi-conducteurs \u00e0 l&rsquo;IMEC, dans un communiqu\u00e9. <\/span><span title=\"&quot;Our work on the test chip has enabled interconnect variation to be measured and improved and the 3nm manufacturing process to be validated.&quot;\n\n\">\u00ab\u00a0Notre travail sur la puce de test a permis de mesurer et d&rsquo;am\u00e9liorer la variabilit\u00e9 d&rsquo;interconnexion et de valider le processus de fabrication 3nm.\u00a0\u00bb<\/span><\/span><\/p>\n<p><span id=\"result_box\" lang=\"fr\"><span title=\"Chin-Chi Teng, corporate vice president at Cadence, said: &quot;Expanding upon the work we did with IMEC in 2015 on the industry's first 5nm tapeout, we are achieving new milestones together with this new 3nm tapeout, which can transform the future of mobile\">Chin-Chi Teng, vice-pr\u00e9sident de Cadence, a d\u00e9clar\u00e9: \u00abEn prolongeant le travail que nous avons r\u00e9alis\u00e9 avec IMEC en 2015 sur la premi\u00e8re conception 5nm de l&rsquo;industrie, nous atteignons ensemble de nouveaux jalons avec cette nouvelle technologie 3nm qui peut transformer le futur de la conceotion de mobiles <\/span><span title=\"designs at advanced nodes.&quot;\">\u00ab\u00a0<\/span><\/span><\/p>\n<p><strong>La r\u00e9daction vous conseille \u00e9galement:<\/strong><\/p>\n<p><a href=\"http:\/\/www.electronique-eci.com\/node\/101525\">MCU avec MRAM made in France<\/a><\/p>\n<p><a href=\"http:\/\/www.electronique-eci.com\/news\/ase-et-cadence-livrent-la-premiere-solution-de-cao-electronique-de-system-package\">ASE et Cadence livrent la premi\u00e8re solution de CAO \u00e9lectronique de \u00ab&nbsp;System-In-Package&nbsp;\u00bb<\/a><\/p>\n<p><a href=\"http:\/\/www.imec.be\">www.imec.be<\/a><\/p>\n<p><a href=\"http:\/\/www.cadence.com\">www.cadence.com<\/a><\/p>\n<p><strong>News articles in English: <\/strong><\/p>\n<p><a href=\"http:\/\/www.eenewsanalog.com\/news\/broadcom-preps-7nm-tape-outs-2017\">Broadcom preps for 7nm tape-outs in 2017<\/a><\/p>\n<p><a href=\"http:\/\/www.eenewsanalog.com\/news\/arm-offers-support-tsmc-7nm-manufacturing\">ARM offers support for TSMC 7nm manufacturing<\/a><\/p>\n<p><a href=\"http:\/\/www.eenewsanalog.com\/news\/irresistible-materials-ramps-production-euv-photoresist\">Irresistible Materials ramps production of EUV photoresist<\/a><\/p>\n<p><a href=\"http:\/\/www.eenewsanalog.com\/Learning-center\/synopsys-foundation-ip-7nm-finfets-design-and-implementation\">Synopsys: Foundation IP for 7nm FinFETs: Design and Implementation <\/a><\/p>\n<p><a href=\"http:\/\/www.eenewsanalog.com\/news\/globalfoundries-launches-7nm-asic-platform\">Globalfoundries launches 7nm ASIC platform <\/a><\/p>\n<p><a href=\"http:\/\/www.eenewsanalog.com\/news\/intel-commits-7bn-7nm-arizona-fab\">Intel commits $7bn to 7nm Arizona fab <\/a><\/p>\n","protected":false},"excerpt":{"rendered":"<p>Nanoelectronics research institure IMEC and EDA software supplier have worked together to produce a tape-out for a 64bit processor core as a test chip to be built in a nominal 3nm node.<br \/>\nL&rsquo;institut de recherche en nano\u00e9lectronique IMEC et le fournisseur de logiciels EDA ont travaill\u00e9 ensemble pour produire le fichier de fabrication pour un c\u0153ur de processeur 64 bits comme circuite test en technologie 3 nm.<\/p>\n","protected":false},"author":22,"featured_media":127917,"comment_status":"closed","ping_status":"closed","sticky":false,"template":"","format":"standard","meta":{"_acf_changed":false,"footnotes":""},"categories":[883],"tags":[899,913,905,906,908],"domains":[47],"ppma_author":[1149],"class_list":["post-127916","post","type-post","status-publish","format-standard","has-post-thumbnail","hentry","category-technologies","tag-eda-cad-tools-fr","tag-materials-processes-fr","tag-memory-data-storage-fr","tag-mpus-mcus-fr","tag-plds-fpgas-asics-fr","domains-electronique-eci"],"acf":[],"yoast_head":"<title>Premiers chips de test 3nm par IMEC et Cadence ...<\/title>\n<meta name=\"description\" content=\"Nanoelectronics research institure IMEC and EDA software supplier have worked together to produce a tape-out for a 64bit processor core as a test chip to be...\" \/>\n<meta name=\"robots\" content=\"index, follow, max-snippet:-1, max-image-preview:large, max-video-preview:-1\" \/>\n<link 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