{"id":126964,"date":"2018-03-19T10:19:44","date_gmt":"2018-03-19T10:19:44","guid":{"rendered":"https:\/\/\/xilinx-prepare-une-architecture-revolutionaire-a-7nm\/"},"modified":"2018-03-19T10:19:44","modified_gmt":"2018-03-19T10:19:44","slug":"xilinx-prepare-une-architecture-revolutionaire-a-7nm","status":"publish","type":"post","link":"https:\/\/www.ecinews.fr\/fr\/xilinx-prepare-une-architecture-revolutionaire-a-7nm\/","title":{"rendered":"Xilinx pr\u00e9pare une architecture r\u00e9volutionaire \u00e0 7nm"},"content":{"rendered":"<p><span id=\"result_box\" lang=\"fr\"><span title=\"At a pre-launch event held in London, recently elected CEO Victor Peng justified the need for the new architecture as a way to circumvent the demise of Moor's law, considering the ACAP as the mother of all future ASICs.\n\n\">Lors d&rsquo;un pr\u00e9-lancement \u00e0 Londres, le PDG r\u00e9cemment \u00e9lu Victor Peng a justifi\u00e9 le besoin de la nouvelle architecture comme un moyen de contourner l&rsquo;obsolecense de la loi de Moore, et consid\u00e8re l&rsquo;ACAP comme la m\u00e8re de tous les futurs ASIC.<\/span><\/span><\/p>\n<p><span id=\"result_box\" lang=\"fr\"><span title=\"&quot;It's not that we don't know how to go to the next node, but the economics of Moor's law have stopped working. Getting better performance or faster devices for cheaper is no longer true&quot;, the CEO said.\">Ce n&rsquo;est pas que nous ne sachions pas comment aller au n\u0153ud suivant, mais l&rsquo;\u00e9conomie de la loi de Moore a cess\u00e9 de fonctionner: obtenir de meilleures performances ou des appareils plus rapides pour toujours moins cher n&rsquo;est plus vrai\u00a0\u00bb, a d\u00e9clar\u00e9 le PDG. <\/span><span title=\"This was hinting at the fact that for ASIC designers, it is becoming increasingly difficult to find the volumes that would justify the fixed value of an ASIC, without the possibility to optimize it for a wide mix of applications.\n\n\">Cela laisse supposer que pour les concepteurs d&rsquo;ASIC, il devient de plus en plus difficile de trouver les volumes qui justifieraient la valeur fixe d&rsquo;un ASIC, sans possibilit\u00e9 de l&rsquo;optimiser pour un large \u00e9ventail d&rsquo;applications.<\/span><\/p>\n<p><span title=\"&quot;The speed of innovation is outpacing silicon design cycles, and what do you do about this challenge?&quot;\">\u00ab\u00a0La vitesse de l&rsquo;innovation est plus rapide que les cycles de conception de silicium, et que pouvons-nous faire pour relever ce d\u00e9fi?\u00a0\u00bb&nbsp;<\/span><span title=\"Peng asked the audience, highlighting the need for adaptable chips.\n\n\"> demande Peng au public, en soulignant le besoin de puces adaptables.<\/span><\/span><\/p>\n<p><span id=\"result_box\" lang=\"fr\"><span title=\"The ACAP was presented as a major technology disruption for the industry, and Xilinx's most significant engineering accomplishment since the invention of the FPGA, no less.\">L&rsquo;ACAP a \u00e9t\u00e9 pr\u00e9sent\u00e9 comme une rupture technologique majeure pour l&rsquo;industrie, et le plus important accomplissement en ing\u00e9nierie de Xilinx depuis l&rsquo;invention du FPGA, rien de moins. <\/span><span title=\"At its core, the ACAP has a new generation of FPGA fabric with distributed memory and hardware-programmable DSP blocks, a multicore SoC, and one or more software programmable, yet hardware adaptable, compute engines, all connected through a network on chip (NoC\">\u00c0 la base, l&rsquo;ACAP dispose d&rsquo;une nouvelle g\u00e9n\u00e9ration de structures FPGA avec m\u00e9moire distribu\u00e9e et blocs DSP programmables par hardware, un SoC multic\u0153ur et un ou plusieurs moteurs de calcul programmables, mais aussi adaptables par hardware, tous connect\u00e9s via un r\u00e9seau sur puce (NoC <\/span><span title=\").\">). <\/span><span title=\"Peng would remain evasive regarding the actual blend of fabric.\">Peng est cependant rest\u00e9 \u00e9vasif en ce qui concerne l&rsquo;assemblege r\u00e9el des structure. <\/span><span title=\"&quot;The way we create the bitstream is completely different, and the NoC enables above GHz flow control&quot; the CEO said later during an interview with eeNews Europe.\n\n\">\u00ab\u00a0La fa\u00e7on dont nous cr\u00e9ons le \u00ab\u00a0bitstream\u00a0\u00bb (flux binaire) est compl\u00e8tement diff\u00e9rent, et le NoC permet un contr\u00f4le de flux sup\u00e9rieur au GHz\u00a0\u00bb, a d\u00e9clar\u00e9 le PDG lors d&rsquo;un entretien avec eeNews Europe. ( publication accoci\u00e9e de ECI)<\/span><\/span><br \/>\n&nbsp;<\/p>\n<p><span id=\"result_box\" lang=\"fr\"><span title=\"The ACAP also has highly integrated programmable I\/O functionality, ranging from integrated hardware programmable memory controllers, advanced SerDes technology and leading edge RF-ADC\/DACs, to integrated High Bandwidth Memory (HBM) depending on the device variant.\">L&rsquo;ACAP dispose \u00e9galement de fonctionnalit\u00e9s d&rsquo;E \/ S programmables hautement int\u00e9gr\u00e9es, allant des contr\u00f4leurs de m\u00e9moire programmables mat\u00e9riels int\u00e9gr\u00e9s, de la technologie SerDes avanc\u00e9e et des ADC \/ DAC de pointe \u00e0 la m\u00e9moire HBM (High Bandwidth Memory) int\u00e9gr\u00e9e selon la variante du composant. <\/span><span title=\"What makes it adaptive is that it can be changed at the hardware level to adapt to the needs of a wide range of applications and workloads, dynamically during operation.\n\n\">Ce qui le rend adaptatif, c&rsquo;est qu&rsquo;il peut \u00eatre modifi\u00e9 au niveau du hardware pour s&rsquo;adapter aux besoins d&rsquo;une large gamme d&rsquo;applications et de charges de travail, de fa\u00e7on dynamique pendant le fonctionnement.<\/span><\/span><\/p>\n<hr \/>\n<p><span id=\"result_box\" lang=\"fr\"><span title=\"This in order to deliver levels of performance orders of magnitude better than today's CPUs, while being adaptable to more use cases than GPUs or ASICs.\">Cel\u00e0 permet de fournir des niveaux de performance sup\u00e9rieurs d&rsquo;une magnitute aux CPU actuels, tout en \u00e9tant adaptable \u00e0 plus de cas d&rsquo;utilisation que les GPU ou les ASIC. <\/span><span title=\"But haven't we heard that on-the-fly reconfigurability story before and what is different this time?\">Mais n&rsquo;avons-nous pas d\u00e9j\u00e0 entendu cette histoire de reconfigurabilit\u00e9 \u00e0 la vol\u00e9e maintes fois?&nbsp; donc que-ce-qu&rsquo;il y a de diff\u00e9rent cette fois-ci? <\/span><span title=\"The ACAP would adapt to multiple workloads on the same piece of silicon, with reconfigurable engines within a novel type of fabric (itself reconfigurable?)\n\n\">L&rsquo;ACAP s&rsquo;adapte \u00e0 de multiples charges de travail sur le m\u00eame surface de silicium, avec des moteurs reconfigurables dans un nouveau type de structures (lui-m\u00eame reconfigurable?)<\/span><\/span><\/p>\n<p><span id=\"result_box\" lang=\"fr\"><span title=\"Could Xilinx be borrowing some of the new fabric elements from FPGA startup Efinix?\">Est-ce que Xilinx pourrait emprunter certains des nouveaux \u00e9l\u00e9ments de structures de la startup FPGA Efinix? <\/span><span title=\"The Californian startup claims a 4x power-performance-area advantage over traditional programmable technologies thanks to the use of blocks that can be configured for routing or logic depending on the circuit being implemented.\">La startup californienne revendique un avantage de 4 foisdu facteur performance\/puissance par rapport aux technologies programmables traditionnelles gr\u00e2ce \u00e0 l&rsquo;utilisation de blocs configurables pour le routage ou la logique en fonction du circuit mis en \u0153uvre. <\/span><span title=\"In September last year, Efinix announced a $9.5M funding round led by Xilinx, bringing its total raised funds to circa $16.5M.\n\n\">En septembre de l&rsquo;ann\u00e9e derni\u00e8re, Efinix a annonc\u00e9 un tour de financement de 9,5 millions de dollars dirig\u00e9 par Xilinx, ce qui porte le total des fonds recueillis \u00e0 environ 16,5 millions de dollars.<\/span><\/span><br \/>\n&nbsp;<\/p>\n<p><span id=\"result_box\" lang=\"fr\"><span title=\"Does that make Xilinx a majority investor and does it give Xilinx some control power over Efinix' roadmap?\">Cela fait-il de Xilinx un investisseur majoritaire et donne-t-il \u00e0 Xilinx un certain pouvoir de contr\u00f4le sur la feuille de route d&rsquo;Efinix? <\/span><span title=\"&quot;All we can confirm is that we have invested in Efinix&quot; was a rather short answer.\n\n\">\u00ab\u00a0Tout ce que nous pouvons confirmer, c&rsquo;est que nous avons investi dans Efinix\u00a0\u00bb \u00e9tait lae r\u00e9ponse plut\u00f4t courte donn\u00e9e&#8230;<\/span><\/p>\n<p><span title=\"Discussing the Effinix investment and various other startups offering to embed FPGA fabrics into ASICs, Peng said that although embedded FPGA was not considered as a prominent innovation strategy for Xilinx, the company could enable it, and if it became strategic, then an acquisition could make\">Parlant de l&rsquo;investissement <a href=\"http:\/\/www.electronique-eci.com\/news\/la-startup-efinix-reinvente-le-fpga\">Effinix<\/a> et de diverses autres startups proposant d&rsquo;int\u00e9grer des FPGA dans les ASIC, Peng a d\u00e9clar\u00e9 que m\u00eame si les FPGA embarqu\u00e9s n&rsquo;\u00e9taient pas consid\u00e9r\u00e9s comme une strat\u00e9gie d&rsquo;innovation importante pour Xilinx, l&rsquo;entreprise pourrait l&rsquo;activer et si elle devenait strat\u00e9gique, et alors une acquisition pourrait avoir du <\/span><span title=\"sense.\">sens. <\/span><span title=\"But for now, Xilinx has merely established a partnership with Effinix who uses Xilinx's tools and coding ecosystem.\n\n\">Mais pour l&rsquo;instant, Xilinx a simplement \u00e9tabli un partenariat avec Effinix qui utilise les outils et l&rsquo;\u00e9cosyst\u00e8me de codage de Xilinx.<\/span><\/span><\/p>\n<p><span id=\"result_box\" lang=\"fr\"><span title=\"&quot;Embedded FPGA doesn't keep me awake at night&quot; the CEO said jokingly, considering this technology segment as negligible competition for a company that expects most of its revenues from high-end FPGAs.\n\">\u00ab\u00a0Le FPGA embarqu\u00e9 ne m&#8217;emp\u00eache pas de dormir la nuit\u00a0\u00bb, a plaisant\u00e9 le PDG, consid\u00e9rant ce segment de la technologie comme une concurrence n\u00e9gligeable pour une entreprise qui attend la plupart de ses revenus des FPGA haut de gamme.<\/span><\/span><br \/>\n&nbsp;<\/p>\n<hr \/>\n<figure class=\"image\" style=\"float:right\"><img decoding=\"async\" alt=\"\" height=\"207\" data-src=\"http:\/\/www.eenewseurope.com\/sites\/default\/files\/images\/01-picture-library\/eenews\/2018\/n-xilinx-interview-3-everest.jpg\" width=\"320\" src=\"data:image\/svg+xml;base64,PHN2ZyB3aWR0aD0iMSIgaGVpZ2h0PSIxIiB4bWxucz0iaHR0cDovL3d3dy53My5vcmcvMjAwMC9zdmciPjwvc3ZnPg==\" class=\"lazyload\" style=\"--smush-placeholder-width: 320px; --smush-placeholder-aspect-ratio: 320\/207;\" \/><figcaption>A block diagram of the ACAP-based Everest.<\/figcaption><\/figure>\n<p><span id=\"result_box\" lang=\"fr\"><span title=\"Going back to the ACAP architecture, it is aimed at a broad set of applications in the emerging era of big data and artificial intelligence and software and hardware developers will be able to design ACAP-based products for end point, edge and cloud applications.\">Pour en revenir \u00e0 l&rsquo;architecture ACAP, il vise un large \u00e9ventail d&rsquo;applications dans l&rsquo;\u00e8re \u00e9mergente du big data et de l&rsquo;intelligence artificielle, et les d\u00e9veloppeurs de logiciels et de mat\u00e9riel pourront concevoir des produits bas\u00e9s sur ACAP pour des applications finales, edge et cloud. <\/span><span title=\"Working on physical implementation, Peng revealed that the first ACAP product family, codenamed \u201cEverest,\u201d would be developed in TSMC 7nm process technology, due to tape out later this year, boasting 50 billion transistors and the result of over one billion dollars of R&amp;D\">Travaillant sur la mise en \u0153uvre physique, Peng a r\u00e9v\u00e9l\u00e9 que la premi\u00e8re famille de produits ACAP, baptis\u00e9e \u00ab\u00a0Everest\u00a0\u00bb, serait d\u00e9velopp\u00e9e dans la technologie TSM 7nm, avec plus de 50 milliards de transistors et plus d&rsquo;un milliard de dollars de d\u00e9penses R &amp; D.<\/span><\/span><br \/>\n&nbsp;<\/p>\n<p><span id=\"result_box\" lang=\"fr\"><span title=\"With this new product line, Xilinx aims to make data centres its priority growth segment, while also accelerating growth in its core markets and taking the lead in what it sees as an emerging adaptive computing era.\n\n\">Avec cette nouvelle ligne de produits, Xilinx vise \u00e0 faire des centres de donn\u00e9es son segment de croissance prioritaire, tout en acc\u00e9l\u00e9rant la croissance de ses principaux march\u00e9s et en prenant la t\u00eate de ce qu&rsquo;elle consid\u00e8re comme une nouvelle \u00e8re de l&rsquo;informatique adaptative.<\/span><\/span><\/p>\n<p><span id=\"result_box\" lang=\"fr\"><span>Les d\u00e9veloppeurs de logiciels seront en mesure de cibler les syst\u00e8mes bas\u00e9s sur ACAP en utilisant des outils tels que C \/ C ++, OpenCL et Python.<\/span> <span>Un ACAP peut \u00e9galement \u00eatre programm\u00e9 au niveau RTL \u00e0 l&rsquo;aide d&rsquo;outils FPGA et Xilinx a d\u00e9clar\u00e9 que plus de 1 500 ing\u00e9nieurs en mat\u00e9riel et logiciel \u00e9taient en train de concevoir \u00abACAP et Everest\u00bb dans l&rsquo;entreprise.<\/span> <span>Des outils logiciels ont \u00e9t\u00e9 livr\u00e9s \u00e0 des clients cl\u00e9s.<\/span> <span>En ce qui concerne les comparaisons de performances, \u00ab\u00a0Everest\u00a0\u00bb devrait atteindre une am\u00e9lioration des performances de 20x sur les r\u00e9seaux neuronaux profonds par rapport au dernier FPGA Virtex VU9P 16nm d&rsquo;aujourd&rsquo;hui et les t\u00eates radio 5G bas\u00e9es sur \u00ab\u00a0Everest\u00a0\u00bb auront 4x la bande passante par rapport aux derni\u00e8res radios 16nm.<\/span><\/span><\/p>\n<p>Xilinx &#8211; <a href=\"http:\/\/www.xilinx.com\">www.xilinx.com<\/a><\/p>\n<p>La r\u00e9daction vous conseille:<\/p>\n<p><a href=\"http:\/\/www.electronique-eci.com\/news\/la-startup-efinix-reinvente-le-fpga\">La Startup Efinix r\u00e9invente le FPGA<\/a><\/p>\n<p>&nbsp;<\/p>\n<p><strong>Related articles in English:<\/strong><\/p>\n<p><a href=\"http:\/\/www.eenewseurope.com\/news\/ceo-change-xilinx-former-coo-victor-peng-replace-retiring-moshe-gavrielov\">CEO change at Xilinx: former COO Victor Peng to replace retiring Moshe Gavrielov<\/a><\/p>\n<p><a href=\"http:\/\/www.eenewseurope.com\/news\/fpga-startup-delivers-first-product\">FPGA startup delivers first product<\/a><\/p>\n<p><a href=\"http:\/\/www.eenewseurope.com\/news\/xilinx-zynq-ultrascale-rfsoc-chips-integrate-rf-signal-chain-0\">Xilinx\u2019 Zynq ultrascale+ RFSoC chips integrate the RF signal chain<\/a><\/p>\n<p><a href=\"http:\/\/www.eenewseurope.com\/news\/fpga-startup-wins-funds-xilinx-samsung\">FPGA startup wins funds from Xilinx, Samsung<\/a><\/p>\n<p><a href=\"http:\/\/www.eenewseurope.com\/news\/xilinx-expands-ecosystem-around-zync-mpsoc\">Xilinx expands ecosystem around Zync MPSoC<\/a><\/p>\n<p>&nbsp;<\/p>\n","protected":false},"excerpt":{"rendered":"<p>En d\u00e9voilant sa plateforme ACAP (Adaptive Compute Acceleration Platform), Xilinx promet une plus grande flexibilit\u00e9 pour l&rsquo;acc\u00e9l\u00e9ration de l&rsquo;IA et une augmentation spectaculaire des performances de calcul gr\u00e2ce \u00e0 une toute nouvelle architecture h\u00e9t\u00e9rog\u00e8ne multic\u0153ur.<\/p>\n","protected":false},"author":22,"featured_media":126965,"comment_status":"closed","ping_status":"closed","sticky":false,"template":"","format":"standard","meta":{"_acf_changed":false,"footnotes":""},"categories":[883],"tags":[908],"domains":[47],"ppma_author":[1149],"class_list":["post-126964","post","type-post","status-publish","format-standard","has-post-thumbnail","hentry","category-technologies","tag-plds-fpgas-asics-fr","domains-electronique-eci"],"acf":[],"yoast_head":"<title>Xilinx pr\u00e9pare une architecture r\u00e9volutionaire \u00e0 7nm ...<\/title>\n<meta name=\"description\" content=\"En d\u00e9voilant sa plateforme ACAP (Adaptive Compute Acceleration Platform), Xilinx promet une plus grande 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