{"id":124152,"date":"2018-04-19T22:31:44","date_gmt":"2018-04-19T22:31:44","guid":{"rendered":"https:\/\/\/cadence-etend-sa-plateforme-virtuoso\/"},"modified":"2018-04-19T22:31:44","modified_gmt":"2018-04-19T22:31:44","slug":"cadence-etend-sa-plateforme-virtuoso","status":"publish","type":"post","link":"https:\/\/www.ecinews.fr\/fr\/cadence-etend-sa-plateforme-virtuoso\/","title":{"rendered":"Cadence \u00e9tend sa plateforme Virtuoso"},"content":{"rendered":"

Une plateforme de conception syst\u00e8me, Virtuoso System Design Platform, enrichie<\/strong><\/p>\n

Certaines des principales am\u00e9liorations apport\u00e9es \u00e0 la plateforme Virtuoso 2018 optimisent les capacit\u00e9s de la plateforme prim\u00e9e Virtuoso System Design Platform lanc\u00e9e l\u2019ann\u00e9e derni\u00e8re<\/a>. La nouvelle version de cette plateforme permet \u00e0 pr\u00e9sent aux ing\u00e9nieurs syst\u00e8me de modifier et d\u2019analyser de mani\u00e8re transparente les syst\u00e8mes h\u00e9t\u00e9rog\u00e8nes les plus complexes. Par ailleurs, les ing\u00e9nieurs de diff\u00e9rentes disciplines (boitier, photonique, circuits analogiques et RF) peuvent travailler sur une unique plateforme et utiliser la totalit\u00e9 des applications de conception de confiance r\u00e9unies sur la plateforme Virtuoso.<\/p>\n

Au c\u0153ur de ce nouvel environnement de conception syst\u00e8me se trouve un ensemble de technologies qui permettent de faire de l\u2019\u00e9dition simultan\u00e9e bien qu\u2019utilisant plusieurs technologies et kits de conception PDK (Process Design Kit). La plateforme assure en outre une interop\u00e9rabilit\u00e9 transparente entre Cadence SiP Layout et l\u2018int\u00e9gralit\u00e9 des technologies d\u2019analyse Sigrity, cr\u00e9ant ainsi un ensemble complet d\u2019outils \u00ab chip to board \u00bb.<\/p>\n

Conception et layout Virtuoso Advanced-Node<\/strong><\/p>\n

Cette nouvelle mouture de la plateforme Virtuoso int\u00e8gre des m\u00e9thodologies pour technologies avanc\u00e9es innovantes, qui acc\u00e9l\u00e8rent les projets r\u00e9alis\u00e9s dans les n\u0153uds de 22 \u00e0 5 nm. En collaborant avec les fondeurs de pointe, ses clients et plusieurs partenaires de son \u00e9cosyst\u00e8me, Cadence a d\u00e9velopp\u00e9 des technologies avanc\u00e9es capables de g\u00e9rer automatiquement la complexit\u00e9 des processus gr\u00e2ce \u00e0 des m\u00e9thodologies innovantes permettant aux ing\u00e9nieurs de se concentrer sur leurs intentions de conception. En ce qui concerne la conception et l\u2019analyse des circuits, des algorithmes statistiques avanc\u00e9s ciblant sp\u00e9cifiquement les conceptions en technologie FinFET permettent de d\u00e9tecter suffisamment les variations de circuits, ce qui r\u00e9duit les d\u00e9lais d\u2019analyse des variations de conception d\u2019environ 20 %.<\/p>\n

Concernant la conception du layout, un syst\u00e8me \u00ab multi-grids \u00bb unique simplifie les r\u00e8gles de conception complexes des fili\u00e8res 7 nm et 5 nm les plus r\u00e9centes tout en permettant aux ing\u00e9nieurs d\u2019augmenter l\u2019utilisation des technologies de placement-routage en vue d\u2019accro\u00eetre de fa\u00e7on significative la productivit\u00e9. L\u2019association de ces techniques et des am\u00e9liorations apport\u00e9es \u00e0 la m\u00e9thodologie avanc\u00e9e divise par plus de 3 les t\u00e2ches de layout dans les conceptions de production en 7 nm.<\/p>\n

Automatisation et m\u00e9thodologies de conception avanc\u00e9e Virtuoso<\/strong><\/p>\n

Cadence a apport\u00e9 plusieurs am\u00e9liorations pour perfectionner la conception et l\u2019analyse des circuits analogiques. Le d\u00e9bit de simulation de la suite Cadence Virtuoso Analog Design Environment (ADE) est acc\u00e9l\u00e9r\u00e9 jusqu\u2019\u00e0 3x gr\u00e2ce \u00e0 une meilleure int\u00e9gration \u00e0 l\u2019outil Cadence Spectre Circuit Simulator, am\u00e9liorant les vitesses de simulation et donnant acc\u00e8s \u00e0 des analyses avanc\u00e9es permettant de minimiser les it\u00e9rations de conception. Des fonctionnalit\u00e9s uniques ont \u00e9t\u00e9 ajout\u00e9es aux capacit\u00e9s de l\u2019outil Virtuoso ADE Verifier afin de centraliser les sp\u00e9cifications \u00e9lectriques multi-domaines, ce qui permet d\u2019acc\u00e9l\u00e9rer la mise en conformit\u00e9 aux normes en vigueur (ISO 26262, par exemple) d\u2019environ 30 %.<\/p>\n

L\u2019environnement Virtuoso Layout \u00e9volue d\u2019une configuration de validation \u00e9lectrique (\u00ab electrically aware \u00bb) vers la premi\u00e8re solution de layout pilot\u00e9e \u00e9lectriquement et par la simulation du march\u00e9 en utilisant des ensembles uniques de technologies \u00ab in-design \u00bb pour assurer l\u2019int\u00e9grit\u00e9 et optimiser les performances des circuits en cours de conception. Cette nouvelle solution de layout pilot\u00e9e par la simulation permet de r\u00e9soudre nombre des probl\u00e8mes d\u2019\u00e9lectromigration (EM) et d\u2019effets parasites qui p\u00e9nalisent les circuits critiques et les conceptions en n\u0153uds technologiques avanc\u00e9s. Pour accro\u00eetre l\u2019automatisation du layout, le nouvel environnement s\u2019enrichit de techniques r\u00e9volutionnaires de planification et de floorplanning hi\u00e9rarchique, ainsi que de nouvelles technologies d\u2019automatisation du placement-routage dans le but d\u2019augmenter la productivit\u00e9 et le d\u00e9bit de conception du layout, tout en raccourcissant les d\u00e9lais d\u2019ex\u00e9cution du layout.<\/p>\n

Compte tenu de la complexit\u00e9 des circuits int\u00e9gr\u00e9s modernes, l\u2019un des principaux d\u00e9fis consiste \u00e0 r\u00e9partir les t\u00e2ches de layout entre les diff\u00e9rents concepteurs. La plateforme Virtuoso dispose d\u00e9sormais d\u2019une fonction novatrice d\u2019\u00e9dition des conceptions concurrentielle et en temps r\u00e9el, ce qui permet aux concepteurs de r\u00e9partir les t\u00e2ches de layout et de proc\u00e9der \u00e0 des explorations de simulation (\u00ab what-if \u00bb). Cette approche est particuli\u00e8rement utile pour corriger les erreurs de r\u00e8gles de dessin (DRC), la finition des circuits int\u00e9gr\u00e9s et le routage manuel.<\/p>\n

Selon Cadence, ce nouvel environnement de layout avec routage manuel et automatique pilot\u00e9 \u00e9lectriquement, la possibilit\u00e9 de modifier des designs en temps r\u00e9el, et les techniques r\u00e9volutionnaires de planification de la conception, permettront ensemble d\u2019am\u00e9liorer la productivit\u00e9 jusqu\u2019\u00e0 50 %.<\/p>\n

\u00ab Bosch con\u00e7oit des syst\u00e8mes critiques dont la fiabilit\u00e9 est le principal crit\u00e8re. Nous avons besoin d\u2019outils de CAO \u00e9lectronique gr\u00e2ce auxquels nos ing\u00e9nieurs peuvent concevoir, analyser et impl\u00e9menter efficacement des circuits conformes \u00e0 nos exigences de fiabilit\u00e9 sans p\u00e9naliser la productivit\u00e9 globale des concepteurs \u00bb, a d\u00e9clar\u00e9 G\u00f6ran Jerke, chef de projet EDA, Bosch. \u00ab Notre collaboration de longue date avec Cadence a men\u00e9 \u00e0 des innovations de premier ordre, tant sur le plan de la v\u00e9rification \u00e9lectrique \u00ab electrically-aware \u00bb que de la nouvelle conception de layout pilot\u00e9e \u00e9lectriquement. \u00bb<\/p>\n

www.cadence.com<\/a><\/p>\n

Premiers chips de test 3nm par IMEC et Cadence<\/a><\/h3>\n

ASE et Cadence livrent la premi\u00e8re solution de CAO \u00e9lectronique de \u00ab System-In-Package \u00bb<\/a><\/h3>\n

Le GPS logiciel de Galileo Satellite Navigation disponible sur processeur Tensilica Fusion F1<\/a><\/h3>\n

 <\/p>\n","protected":false},"excerpt":{"rendered":"

Soucieux d\u2019am\u00e9liorer la productivit\u00e9 des syst\u00e8mes \u00e9lectroniques et de la conception de circuits int\u00e9gr\u00e9s, Cadence Design Systems a apport\u00e9 des am\u00e9liorations majeures \u00e0 sa plateforme de conception de circuits int\u00e9gr\u00e9s \u00ab custom \u00bb Cadence Virtuoso. Ces am\u00e9liorations concernent la quasi-totalit\u00e9 des produits Virtuoso, fournissant aux ing\u00e9nieurs syst\u00e8me un environnement et un \u00e9cosyst\u00e8me robustes pour concevoir, impl\u00e9menter et analyser des circuits int\u00e9gr\u00e9s, des bo\u00eetiers, des cartes \u00e9lectroniques et des syst\u00e8mes complexes.<\/p>\n","protected":false},"author":9,"featured_media":124153,"comment_status":"closed","ping_status":"closed","sticky":false,"template":"","format":"standard","meta":{"_acf_changed":false,"footnotes":""},"categories":[881],"tags":[],"domains":[47],"ppma_author":[1141],"class_list":["post-124152","post","type-post","status-publish","format-standard","has-post-thumbnail","hentry","category-nouveaux-produits","domains-electronique-eci"],"acf":[],"yoast_head":"Cadence \u00e9tend sa plateforme Virtuoso ...<\/title>\n<meta name=\"description\" content=\"Soucieux d\u2019am\u00e9liorer la productivit\u00e9 des syst\u00e8mes \u00e9lectroniques et de la conception de circuits int\u00e9gr\u00e9s, Cadence Design Systems a apport\u00e9 des...\" \/>\n<meta name=\"robots\" content=\"index, follow, max-snippet:-1, max-image-preview:large, max-video-preview:-1\" \/>\n<link rel=\"canonical\" href=\"https:\/\/www.ecinews.fr\/fr\/wp-json\/wp\/v2\/posts\/124152\/\" \/>\n<meta property=\"og:locale\" content=\"fr_FR\" \/>\n<meta property=\"og:type\" content=\"article\" \/>\n<meta property=\"og:title\" content=\"Cadence \u00e9tend sa plateforme Virtuoso\" \/>\n<meta property=\"og:description\" content=\"Soucieux d\u2019am\u00e9liorer la productivit\u00e9 des syst\u00e8mes \u00e9lectroniques et de la conception de circuits int\u00e9gr\u00e9s, Cadence Design Systems a apport\u00e9 des am\u00e9liorations majeures \u00e0 sa plateforme de conception de circuits int\u00e9gr\u00e9s \u00ab custom \u00bb Cadence Virtuoso. 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