{"id":121604,"date":"2018-05-13T16:07:26","date_gmt":"2018-05-13T16:07:26","guid":{"rendered":"https:\/\/\/intel-retarde-a-nouveau-le-passage-au-10-nm\/"},"modified":"2018-05-13T16:07:26","modified_gmt":"2018-05-13T16:07:26","slug":"intel-retarde-a-nouveau-le-passage-au-10-nm","status":"publish","type":"post","link":"https:\/\/www.ecinews.fr\/fr\/intel-retarde-a-nouveau-le-passage-au-10-nm\/","title":{"rendered":"Intel retarde \u00e0 nouveau le passage au 10 nm"},"content":{"rendered":"<p><span id=\"result_box\" lang=\"fr\"><span title=\"\u201cWe are shipping in low volume and yields are improving, though the rate of improvement is slower than we anticipated,\u201d said Brian Krzanich, Intel\u2019s chief executive, in a conference call with financial analysts.\">\u00ab\u00a0Nous exp\u00e9dions en faible volume et les rendements s&rsquo;am\u00e9liorent, m\u00eame si le rythme d&rsquo;am\u00e9lioration est plus lent que pr\u00e9vu\u00a0\u00bb, a d\u00e9clar\u00e9 Brian Krzanich, directeur g\u00e9n\u00e9ral d&rsquo;Intel, lors d&rsquo;une conf\u00e9rence t\u00e9l\u00e9phonique avec des analystes financiers. <\/span><span title=\"\u201cWe understand the yield issues and have defined improvements for them, but they will take time to implement and qualify.\u201d\n\n\">\u00ab\u00a0Nous comprenons o\u00f9 sont les probl\u00e8mes de rendement et nous avons d\u00e9fini les am\u00e9liorations n\u00e9cessaires, mais cela prendra du temps \u00e0 mettre en \u0153uvre.\u00a0\u00bb<\/span><\/span><br \/>\n&nbsp;<\/p>\n<p><span id=\"result_box\" lang=\"fr\"><span title=\"Intel became the world\u2019s largest maker of computer processors by following the tenets of Moore\u2019s Law, which says that the number of transistors that can be placed on a single silicon chip doubles roughly every two years.\">Intel est devenu le plus grand fabricant mondial de processeurs en suivant les principes de la loi de Moore, qui stipule que le nombre de transistors pouvant \u00eatre plac\u00e9s sur une seule puce de silicium double environ tous les deux ans. <\/span><span title=\"But the company has fallen behind the prescribed pace, with every new generation of chips separated by about three years.\n\">Mais la soci\u00e9t\u00e9 a pris du retard par rapport au rythme prescrit avec chaque nouvelle g\u00e9n\u00e9ration de puces s\u00e9par\u00e9es d&rsquo;environ trois ans (au lieu de deux).<\/span><br \/>\n<span title=\"(Image courtesy of Intel).\n\n\">(Image reproduite avec l&rsquo;aimable autorisation d&rsquo;Intel)<\/span><\/span><\/p>\n<p>&nbsp;<\/p>\n<p>&nbsp;<\/p>\n<figure class=\"image\" style=\"float:left\"><img decoding=\"async\" alt=\"\" height=\"156\" data-src=\"http:\/\/www.eenewseurope.com\/sites\/default\/files\/images\/01-picture-library\/eenews\/2018\/n-intel-10nm.jpg\" width=\"300\" src=\"data:image\/svg+xml;base64,PHN2ZyB3aWR0aD0iMSIgaGVpZ2h0PSIxIiB4bWxucz0iaHR0cDovL3d3dy53My5vcmcvMjAwMC9zdmciPjwvc3ZnPg==\" class=\"lazyload\" style=\"--smush-placeholder-width: 300px; --smush-placeholder-aspect-ratio: 300\/156;\" \/><figcaption><\/figcaption><\/figure>\n<p>&nbsp;<\/p>\n<p><span id=\"result_box\" lang=\"fr\"><span title=\"The 10nm problems are the latest setback for the Santa Clara, California-based company, which has long used manufacturing prowess to stay ahead of rivals like Taiwan Semiconductor Manufacturing Corporation.\">Les probl\u00e8mes \u00e0 10nm sont le dernier revers pour la soci\u00e9t\u00e9 bas\u00e9e \u00e0 Santa Clara, en Californie, qui a longtemps utilis\u00e9 les prouesses de fabrication pour rester en t\u00eate devant des rivaux comme Taiwan Semiconductor Manufacturing Corporation. <\/span><span title=\"Under pressure from customers and investors, Intel has also been forced to update its tick-tock development model.\">Intel avait annonc\u00e9 qu&rsquo;il livrerait le processus 10nm au premier semestre 2016, mais ne cesse de repousser la date d&rsquo;\u00e9ch\u00e9ance.Sous la pression des clients et des investisseurs, Intel a \u00e9galement \u00e9t\u00e9 contraint de mettre \u00e0 jour son mod\u00e8le de d\u00e9veloppement de tic-tac. <\/span><span title=\"For almost a decade, it has followed up every new process technology with a new processor architecture, which is reflected by an \u201c+\u201d in the node name.\">Depuis pr\u00e8s d&rsquo;une d\u00e9cennie, il a accompagn\u00e9 chaque nouvelle technologie de processus d&rsquo;une nouvelle architecture de processeur, qui se traduit par un \u00ab+\u00bb dans le nom du n\u0153ud. <\/span><span title=\"But in 2016, Intel added another step to the model, in which it optimizes the architecture.\n\n\">Mais en 2016, Intel a ajout\u00e9 une nouvelle \u00e9tape au mod\u00e8le, dans lequel il optimise l&rsquo;architecture.<\/span><\/span><\/p>\n<p><span id=\"result_box\" lang=\"fr\"><span title=\"Currently, Intel makes chips based on 14nm+ technology.\">Actuellement, Intel fabrique des puces bas\u00e9es sur la technologie 14nm +. <\/span><span title=\"But in the second half of the year, the company plans to release two new lines of chips likely based on 14nm++ technology.\">Mais dans la seconde moiti\u00e9 de l&rsquo;ann\u00e9e, la soci\u00e9t\u00e9 pr\u00e9voit de lancer deux nouvelles lignes de puces probablement bas\u00e9es sur la technologie 14nm ++. <\/span><span title=\"The product lines are Whiskey Lake for personal computers and Cascade Lake for data centers.\">Les gammes de produits sont Whiskey Lake pour les ordinateurs personnels et Cascade Lake pour les centres de donn\u00e9es. <\/span><span title=\"That technology will provide 70 percent more performance than the original 14nm process.\">Cette technologie fournira 70% de performance en plus que le processus original 14nm.<\/span><\/span><\/p>\n<p>\u00e0 suivre:<\/p>\n<hr \/>\n<p>&nbsp;<\/p>\n<p><span id=\"result_box\" lang=\"fr\"><span title=\"\u201cIf anybody else had 70 percent improvement on a technology node, they might just rename the node,\u201d Krzanich said on the conference call.\">\u00ab\u00a0Si quelqu&rsquo;un d&rsquo;autre obtenait 70% d&rsquo;am\u00e9lioration sur un n\u0153ud technologique, il ne renommerait sans doute le n\u0153ud\u00a0\u00bb, a d\u00e9clar\u00e9 M. Krzanich lors de la conf\u00e9rence t\u00e9l\u00e9phonique. <\/span><span title=\"\u201cAnd we have always chosen to be really transparent and just say, it is an improvement on an existing technology, rather than renaming [the node].\u201d\n\n\">\u00ab\u00a0Et nous avons toujours choisi d&rsquo;\u00eatre vraiment transparent et de dire simplement que c&rsquo;est une am\u00e9lioration par rapport \u00e0 une technologie existante, plut\u00f4t que de renommer [le n\u0153ud].<\/span><\/span><\/p>\n<p><span id=\"result_box\" lang=\"fr\"><span title=\"Manufacturing issues stand in the way of the Intel\u2019s next generation of chips.\">Des probl\u00e8mes de fabrication font obstacle \u00e0 la prochaine g\u00e9n\u00e9ration de puces d&rsquo;Intel. <\/span><span title=\"Intel still employs a technology called deep ultraviolet lithography, which shoots intense beams of light onto silicon wafers, etching patterns where the light touches down.\">Intel utilise encore une technologie appel\u00e9e lithographie par ultraviolets profonds, qui projette des faisceaux de lumi\u00e8re intenses sur des plaquettes de silicium, g\u00e9n\u00e9rant des motifs de gravure l\u00e0 o\u00f9 la lumi\u00e8re se pose. <\/span><span title=\"To produce smaller transistors, it uses a technique called multi-patterning, which adds several steps to the process, raising the risk of defects.\n\n\">Pour produire des transistors plus petits, il utilise une technique appel\u00e9e multi-patterning, qui ajoute plusieurs \u00e9tapes au processus, ce qui augmente le risque de d\u00e9fauts.<\/span><\/span><\/p>\n<p><span id=\"result_box\" lang=\"fr\"><span title=\"The more defects there are on silicon wafers, the lower the yield.\">Plus il y a de d\u00e9fauts sur les plaquettes de silicium, plus le rendement est faible. <\/span><span title=\"Intel needs to eliminate the errors to keep manufacturing costs in check.\">Intel doit \u00e9liminer ces erreurs pour contr\u00f4ler les co\u00fbts de fabrication. <\/span><span title=\"This is the company\u2019s last generation of chips before it shifts to extreme ultraviolet (EUV) lithography, which can condense the number of patterning steps by using smaller wavelengths of light.\n\n\">Il s&rsquo;agit de la derni\u00e8re g\u00e9n\u00e9ration de puces de l&rsquo;entreprise avant de passer \u00e0 la lithographie ultraviolette extr\u00eame (EUV), qui peut condenser le nombre d&rsquo;\u00e9tapes de \u00ab\u00a0patterning\u00a0\u00bb en utilisant des longueurs d&rsquo;onde de lumi\u00e8re plus faibles<\/span><\/span><span lang=\"fr\"><span title=\"This is the company\u2019s last generation of chips before it shifts to extreme ultraviolet (EUV) lithography, which can condense the number of patterning steps by using smaller wavelengths of light.\n\n\">.<\/span><\/span><\/p>\n<p><span id=\"result_box\" lang=\"fr\"><span title=\"In the meantime, competitors are nipping at Intel's heels.\">Dans le m\u00eame temps, les concurrents sont arriv\u00e9s dans les talons d&rsquo;Intel. <\/span><span title=\"The two largest foundries in the world, TSMC and GlobalFoundries, both recently started volume production of chips based on 7nm processes.\">Les deux plus grandes fonderies au monde, TSMC et GlobalFoundries, ont r\u00e9cemment commenc\u00e9 la production en s\u00e9rie de puces bas\u00e9es sur des processus de 7 nm. <\/span><span title=\"And analysts say that technology could compete closely with Intel's 10nm technology, which is speedier but likely costs slightly more per transistor.\">Et les analystes disent que leur technologie pourrait rivaliser avec la technologie 10nm d&rsquo;Intel, qui est plus rapide mais co\u00fbte probablement un peu plus cher par transistor. <\/span><span title=\"Samsung is also working on 7nm manufacturing.\n\n\">Samsung travaille \u00e9galement sur la fabrication 7nm.<\/span><\/span><\/p>\n<p><span id=\"result_box\" lang=\"fr\"><span title=\"\u201cAs Intel\u2019s 10nm process lags further behind schedule, the company\u2019s once formidable manufacturing advantage is disappearing,\u201d Linley Gwennap, principal analyst for The Linley Group, wrote in a recent newsletter.\">\u00ab\u00a0Alors que le processus 10nm d&rsquo;Intel est encore plus len retard que pr\u00e9vu, l&rsquo;ancien avantage industriel de la soci\u00e9t\u00e9 est en train de dispara\u00eetre\u00a0\u00bb, a \u00e9crit Linley Gwennap, analyste principal chez The Linley Group, dans un r\u00e9cent bulletin. <\/span><span title=\"\u201cIntel can no longer count on superior manufacturing technology to give its products an edge in the market.\u201d\n\n\">\u00ab\u00a0Intel ne peut plus compter sur une technologie de fabrication sup\u00e9rieure pour donner \u00e0 ses produits un avantage sur le march\u00e9.\u00a0\u00bb<\/span><\/span><\/p>\n<p><span id=\"result_box\" lang=\"fr\"><span title=\"Intel said that its 10nm process can etch 100.8 million transistors onto each square millimeter of silicon, a metric that the company has pushed as a potential new benchmark for the semiconductor industry.\">Intel a d\u00e9clar\u00e9 que son processus 10nm peut graver 100,8 millions de transistors sur chaque millim\u00e8tre carr\u00e9 de silicium, une mesure que la soci\u00e9t\u00e9 a pouss\u00e9 comme une nouvelle r\u00e9f\u00e9rence pour l&rsquo;industrie des semi-conducteurs. <\/span><span title=\"New benchmarks are probably needed because node names no longer line up with transistors features.\n\n\">De nouveaux benchmarks sont probablement n\u00e9cessaires car les noms de n\u0153uds ne sont plus en ligne avec les fonctionnalit\u00e9s des transistors.<\/span><\/span><\/p>\n<p><span id=\"result_box\" lang=\"fr\"><span title=\"Intel has been trying to offset the end of Moore\u2019s Law with advances in transistor density.\">Intel a essay\u00e9 de compenser la fin de la loi de Moore par des progr\u00e8s dans la densit\u00e9 des transistors. <\/span><span title=\"The transistors inside Intel\u2019s 14nm chips can be packed 2.4 times tighter than they can inside Intel\u2019s previous generation of chips based on the 20nm process.\">Les transistors \u00e0 l&rsquo;int\u00e9rieur des puces 14nm d&rsquo;Intel peuvent avoir une densit\u00e9 de placement 2,4 fois sup\u00e9rieure \u00e0 celle de la g\u00e9n\u00e9ration pr\u00e9c\u00e9dente bas\u00e9e sur le processus 20nm. <\/span><span title=\"The company is aiming to aggressively boost the transistor density another 2.7 times with its 10nm node, Krzanich said.\n\n\">La compagnie vise \u00e0 amplifier agressivement la densit\u00e9 des transistors encore 2.7 fois avec son noeud 10nm, a dit Krzanich.<\/span><\/span><br \/>\n&nbsp;<\/p>\n<p><strong>La r\u00e9daction vous conseille:<\/strong><\/p>\n<p><a href=\"http:\/\/www.electronique-eci.com\/news\/pourquoi-intel-va-revendre-wind-river\"><strong>Pourquoi Intel va revendre Wind River<\/strong><\/a><\/p>\n<p><a href=\"http:\/\/www.electronique-eci.com\/news\/samsung-champion-2017-des-fabricants-de-puces\"><strong>Samsung, champion 2017 des fabricants de puces<\/strong><\/a><\/p>\n<p>&nbsp;<\/p>\n","protected":false},"excerpt":{"rendered":"<p>Les affaires d&rsquo;Intel tirent sur tous les cylindres mais la loi de Moore a des rat\u00e9s. La soci\u00e9t\u00e9, qui a r\u00e9cemment annonc\u00e9 un chiffre d&rsquo;affaires Q1 de 1 milliard de dollars sup\u00e9rieur aux estimations de Wall Street, a d\u00e9cid\u00e9 de r\u00e9initialiser le timing de son n\u0153ud de processus de prochaine g\u00e9n\u00e9ration \u00e0 10 nanom\u00e8tres. Intel a d\u00e9clar\u00e9 que la production en volume serait repouss\u00e9 de la seconde moiti\u00e9 de 2018 \u00e0 2019.<\/p>\n","protected":false},"author":22,"featured_media":121605,"comment_status":"closed","ping_status":"closed","sticky":false,"template":"","format":"standard","meta":{"_acf_changed":false,"footnotes":""},"categories":[883],"tags":[913],"domains":[47],"ppma_author":[1149],"class_list":["post-121604","post","type-post","status-publish","format-standard","has-post-thumbnail","hentry","category-technologies","tag-materials-processes-fr","domains-electronique-eci"],"acf":[],"yoast_head":"<title>Intel retarde \u00e0 nouveau le passage au 10 nm ...<\/title>\n<meta name=\"description\" content=\"Les affaires d&#039;Intel tirent sur tous les cylindres mais la loi de Moore a des rat\u00e9s. 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La soci\u00e9t\u00e9, qui a r\u00e9cemment annonc\u00e9 un chiffre d'affaires Q1 de 1...","robots":{"index":"index","follow":"follow","max-snippet":"max-snippet:-1","max-image-preview":"max-image-preview:large","max-video-preview":"max-video-preview:-1"},"canonical":"https:\/\/www.ecinews.fr\/fr\/wp-json\/wp\/v2\/posts\/121604\/","og_locale":"fr_FR","og_type":"article","og_title":"Intel retarde \u00e0 nouveau le passage au 10 nm","og_description":"Les affaires d'Intel tirent sur tous les cylindres mais la loi de Moore a des rat\u00e9s. La soci\u00e9t\u00e9, qui a r\u00e9cemment annonc\u00e9 un chiffre d'affaires Q1 de 1 milliard de dollars sup\u00e9rieur aux estimations de Wall Street, a d\u00e9cid\u00e9 de r\u00e9initialiser le timing de son n\u0153ud de processus de prochaine g\u00e9n\u00e9ration \u00e0 10 nanom\u00e8tres. Intel a d\u00e9clar\u00e9 que la production en volume serait repouss\u00e9 de la seconde moiti\u00e9 de 2018 \u00e0 2019.","og_url":"https:\/\/www.ecinews.fr\/fr\/wp-json\/wp\/v2\/posts\/121604\/","og_site_name":"EENewsEurope","article_published_time":"2018-05-13T16:07:26+00:00","og_image":[{"width":1540,"height":800,"url":"https:\/\/www.ecinews.fr\/wp-content\/uploads\/import\/default\/files\/sites\/default\/files\/images\/n-intel-10nm.jpg","type":"image\/jpeg"}],"author":"eeNews Europe","twitter_card":"summary_large_image","twitter_misc":{"Written by":"eeNews Europe","Est. reading time":"4 minutes"},"schema":{"@context":"https:\/\/schema.org","@graph":[{"@type":"Article","@id":"https:\/\/www.ecinews.fr\/fr\/intel-retarde-a-nouveau-le-passage-au-10-nm\/#article","isPartOf":{"@id":"https:\/\/www.ecinews.fr\/fr\/intel-retarde-a-nouveau-le-passage-au-10-nm\/"},"author":{"name":"eeNews Europe","@id":"https:\/\/www.eenewseurope.com\/en\/#\/schema\/person\/9eff4051fa9dac8230052de45e32b0f4"},"headline":"Intel retarde \u00e0 nouveau le passage au 10 nm","datePublished":"2018-05-13T16:07:26+00:00","dateModified":"2018-05-13T16:07:26+00:00","mainEntityOfPage":{"@id":"https:\/\/www.ecinews.fr\/fr\/intel-retarde-a-nouveau-le-passage-au-10-nm\/"},"wordCount":897,"publisher":{"@id":"https:\/\/www.eenewseurope.com\/en\/#organization"},"keywords":["Materials &amp; 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