{"id":10763,"date":"2021-06-02T15:52:07","date_gmt":"2021-06-02T15:52:07","guid":{"rendered":"https:\/\/\/tsmc-contre-attaque-sur-le-marche-de-la-fonderie\/"},"modified":"2021-06-02T15:52:07","modified_gmt":"2021-06-02T15:52:07","slug":"tsmc-contre-attaque-sur-le-marche-de-la-fonderie","status":"publish","type":"post","link":"https:\/\/www.ecinews.fr\/fr\/tsmc-contre-attaque-sur-le-marche-de-la-fonderie\/","title":{"rendered":"TSMC contre-attaque sur le march\u00e9 de la fonderie"},"content":{"rendered":"<p><!-- Global site tag (gtag.js) - Google Analytics --><\/p>\n<p>\u00a0 window.dataLayer = window.dataLayer || [];<\/p>\n<p>\u00a0 function gtag(){dataLayer.push(arguments);}<\/p>\n<p>\u00a0 gtag(&lsquo;js&rsquo;, new Date());\u00a0 gtag(&lsquo;config&rsquo;, &lsquo;UA-160857065-1&rsquo;);<\/p>\n<p class=\"MsoNormal\">Les cadres sup\u00e9rieurs de TSMC \u00e0 Ta\u00efwan et en Europe ont soulign\u00e9 le fait que l&rsquo;entreprise n&rsquo;est pas en concurrence avec ses clients. \u00ab\u00a0Nous ne sommes pas en concurrence avec vous, nous sommes une fonderie pureplay\u00a0\u00bb, a d\u00e9clar\u00e9 aujourd&rsquo;hui Maria Marced, pr\u00e9sidente de TSMC Europe BV lors du symposium technologique TSMC le 2 juin 2021.<\/p>\n<p class=\"MsoNormal\">Cette d\u00e9claration&nbsp;intervient alors que la soci\u00e9t\u00e9 se pr\u00e9pare \u00e0 la mise en production de sa technologie de process&nbsp;3 nm plus tard cette ann\u00e9e et \u00e0 la production de masse au second semestre 2022. La soci\u00e9t\u00e9 ne voulait pas faire de&nbsp;commentaire&nbsp;sur son calendrier pour sa technologie de process&nbsp;2 nm.<\/p>\n<p class=\"MsoNormal\">\n<p>\u00ab\u00a0Nous n&rsquo;aurons jamais nos propres produits en concurrence avec les v\u00f4tres\u00a0\u00bb, a d\u00e9clar\u00e9 CC Wei, PDG de TSMC lors du m\u00eame \u00e9v\u00e9nement. Il a \u00e9galement soulign\u00e9 l&rsquo;investissement de 100 milliards de dollars pr\u00e9c\u00e9demment annonc\u00e9 dans la capacit\u00e9 de production de TSMC pour rassurer les clients sur les p\u00e9nuries actuelles.<\/p>\n<p>La soci\u00e9t\u00e9 lance un process&nbsp;de 5 nm pour les conceptions automobiles ainsi qu&rsquo;une variante pour les puces RF. Elle \u00e9tend \u00e9galement sa capacit\u00e9 de packaging&nbsp;3D qui remplit actuellement cinq usines d\u00e9di\u00e9es \u00e0 Ta\u00efwan.<\/p>\n<p class=\"MsoNormal\">\u00ab&nbsp;Nous avons \u00e9tendu N5 \u00e0 l&rsquo;automobile sur N5A pour r\u00e9pondre \u00e0 la demande d&rsquo;assistance \u00e0 la conduite bas\u00e9e sur l&rsquo;IA et \u00e0 la num\u00e9risation des cockpits de v\u00e9hicules. N5A combine le process&nbsp;5 nm \u00e0 haut volume avec les exigences de fiabilit\u00e9 de l&rsquo;AEC-Q100 Grade 2 ainsi que d&rsquo;autres normes de s\u00e9curit\u00e9 et de qualit\u00e9 automobiles \u00bb, a d\u00e9clar\u00e9 Wei.<span>&nbsp;<\/span><\/p>\n<p>N5A devrait \u00eatre disponible au troisi\u00e8me trimestre 2022.<\/p>\n<p class=\"MsoNormal\"><strong>Related TSMC articles<\/strong><\/p>\n<ul>\n<li class=\"MsoNormal\"><span class=\"MsoHyperlink\"><a href=\"https:\/\/www.eenewseurope.com\/news\/tsmc-calls-eu-semiconductor-boost-unrealistic\">EU semiconductor boost &lsquo;unrealistic&rsquo;<\/a><\/span><\/li>\n<li class=\"MsoNormal\"><span class=\"MsoHyperlink\"><a href=\"https:\/\/www.eenewseurope.com\/news\/intel-TSMC-5nm\">Intel outsources Core i3 to N5&nbsp;process<\/a><\/span><\/li>\n<li class=\"MsoNormal\"><span class=\"MsoHyperlink\"><a href=\"https:\/\/www.eenewseurope.com\/news\/intel-goes-full-foundry\">Intel goes full foundry<\/a><\/span><\/li>\n<li class=\"MsoNormal\"><span class=\"MsoHyperlink\"><a href=\"https:\/\/www.eenewseurope.com\/news\/tsmcs-100bn-fab-plans-expand-capacity\">$100bn fab plans to expand capacity<\/a><\/span><\/li>\n<li class=\"MsoNormal\"><span class=\"MsoHyperlink\"><a href=\"https:\/\/www.eenewseurope.com\/news\/tsmc-looks-2nm-process-technology\">Looking&nbsp;to 2nm process technology<\/a><\/span> <\/li>\n<\/ul>\n<p class=\"MsoNormal\">Un r\u00e9tr\u00e9cissement optique du process&nbsp;5 nm est pr\u00e9vu pour une production pr\u00e9coce plus tard cette ann\u00e9e. N4 offre une am\u00e9lioration de la densit\u00e9 de 6% avec des r\u00e8gles de conception compatibles avec N5 ainsi qu&rsquo;une r\u00e9duction du nombre de masques pour r\u00e9duire les co\u00fbts. La production avec&nbsp;risques est fix\u00e9e au troisi\u00e8me trimestre 2021.<\/p>\n<p class=\"MsoNormal\">Pour les smartphones 5G, TSMC a pr\u00e9sent\u00e9 le processus N6RF, qui apporte des avantages en termes de puissance, de performances et de surface du process&nbsp;logique 6 nm aux puces radiofr\u00e9quence (RF) 5G, inf\u00e9rieures \u00e0 6 GHz et \u00e0 ondes millim\u00e9triques, ainsi qu&rsquo;aux conceptions WiFi 6\/6e. Ceci est destin\u00e9 aux conceptions actuellement sur un processus de 16 nm et augmenterait la fr\u00e9quence de coupure de 257 GHz en 16FFC \u00e0 310 GHz avec une r\u00e9duction de consommation&nbsp;de 40 %.<\/p>\n<p class=\"MsoNormal\">\n<p>Pour les applications de calcul hautes performances, en particulier de AMD,&nbsp;concurrent d&rsquo;Intel, TSMC proposera une plus grande taille de r\u00e9ticule pour ses technologies de packaging&nbsp;InFO_oS et CoWoS plus tard cette ann\u00e9e. Cela permettra des surfaces&nbsp;plus grandes pour l&rsquo;int\u00e9gration de chiplets et de m\u00e9moire \u00e0 large bande passante. De plus, la version chip-on-wafer (CoW) de TSMC-SoI\u2122 sera qualifi\u00e9e sur N7-on-N7 cette ann\u00e9e avec une production pr\u00e9vue pour 2022 dans une nouvelle usine enti\u00e8rement automatis\u00e9e.<\/p>\n<p>Pour les applications mobiles, TSMC pr\u00e9sente sa technologie de packaging&nbsp;InFO_B pour int\u00e9grer un puissant processeur mobile avec empilement de DRAM sur sur le bo\u00eetier.<\/p>\n<p class=\"MsoNormal\"><strong>Lire aussi:<\/strong><\/p>\n<p class=\"MsoNormal\"><a href=\"https:\/\/www.ecinews.fr\/news\/intel-reclame-8-milliards-deuros-daides-pour-construire-eurofab\"><strong>Intel r\u00e9clame 8 milliards d&rsquo;euros d&rsquo;aides pour construire EuroFab<\/strong><\/a><\/p>\n<p class=\"MsoNormal\" style=\"margin: 0px 0px 10px;, sans-serif;font-size: 16px;font-style: normal;font-weight: 400;letter-spacing: normal;text-align: start;text-indent: 0px;text-transform: none\"><span style=\"font-size:14px\"><u><a href=\"https:\/\/www.ecinews.fr\/news\/leurope-doit-sortir-de-ses-30-ans-de-sommeil-dans-les-semiconducteurs\" style=\"background: transparent;text-decoration: none\"><strong style=\"font-weight: bold\">L&rsquo;Europe doit sortir de ses 30 ans de sommeil dans les semiconducteurs <\/strong><\/a><\/u><\/span><\/p>\n<p class=\"MsoNormal\" style=\"margin: 0px 0px 10px;, sans-serif;font-size: 16px;font-style: normal;font-weight: 400;letter-spacing: normal;text-align: start;text-indent: 0px;text-transform: none\"><span style=\"font-size:14px\"><u><a href=\"https:\/\/www.ecinews.fr\/news\/le-defi-de-leurope-des-semiconducteurs\" style=\"background: transparent;text-decoration: none\"><strong style=\"font-weight: bold\">Le d\u00e9fi de l&rsquo;Europe des semiconducteurs <\/strong><\/a><\/u><\/span><\/p>\n<p class=\"MsoNormal\" style=\"margin: 0px 0px 10px;, sans-serif;font-size: 16px;font-style: normal;font-weight: 400;letter-spacing: normal;text-align: start;text-indent: 0px;text-transform: none\"><span style=\"font-size:14px\"><u><a href=\"https:\/\/www.ecinews.fr\/news\/intel-sous-traite-la-fabrication-de-ses-core-i3-5nm-tsmc\" style=\"background: transparent;text-decoration: none\"><strong style=\"font-weight: bold\">Intel sous-traite la fabrication de ses Core i3 5nm \u00e0 TSMC <\/strong><\/a><\/u><\/span><\/p>\n<p class=\"MsoNormal\">\n<p class=\"MsoNormal\"><a href=\"http:\/\/www.tsmc.com\">www.tsmc.com<\/a>&nbsp;<\/p>\n<p class=\"MsoNormal\"><strong>Other related articles<\/strong><\/p>\n<ul>\n<li class=\"MsoNormal\"><a href=\"https:\/\/www.eenewseurope.com\/news\/g7-discuss-chip-supply-cornwall\">G7 to discuss chip supply in Cornwall<\/a><\/li>\n<li class=\"MsoNormal\"><span class=\"MsoHyperlink\"><a href=\"https:\/\/www.eenewseurope.com\/news\/mit-charts-path-1nm-chips\">MIT charts path to 1nm chips<\/a><\/span><\/li>\n<li class=\"MsoNormal\"><span class=\"MsoHyperlink\"><a href=\"https:\/\/www.eenewseurope.com\/news\/ibm-shows-first-2nm-chip\">IBM shows first chip built on a 2nm process<\/a><\/span><\/li>\n<li class=\"MsoNormal\"><a href=\"https:\/\/www.eenewseurope.com\/news\/synopsys-ports-moortec-pvt-sensor-3nm\">Synopsys ports Moortec PVT sensor to 3nm<\/a><\/li>\n<\/ul>\n<ul>\n<li class=\"MsoNormal\">\n<hr \/>\n<\/li>\n<\/ul>\n<p class=\"MsoNormal\">\n","protected":false},"excerpt":{"rendered":"<p>TSMC a mis en avant son r\u00f4le de fonderie pure-play pour minimiser la concurrence d&rsquo;Intel.<\/p>\n","protected":false},"author":7,"featured_media":10764,"comment_status":"open","ping_status":"closed","sticky":false,"template":"","format":"standard","meta":{"_acf_changed":false,"footnotes":""},"categories":[880],"tags":[899,913],"domains":[47],"ppma_author":[1139],"class_list":["post-10763","post","type-post","status-publish","format-standard","has-post-thumbnail","hentry","category-actualites-economiques","tag-eda-cad-tools-fr","tag-materials-processes-fr","domains-electronique-eci"],"acf":[],"yoast_head":"<title>TSMC contre-attaque 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