{"id":100620,"date":"2018-12-10T23:00:44","date_gmt":"2018-12-10T23:00:44","guid":{"rendered":"https:\/\/\/fpga-soc-a-architecture-risc-v\/"},"modified":"2018-12-10T23:00:44","modified_gmt":"2018-12-10T23:00:44","slug":"fpga-soc-a-architecture-risc-v","status":"publish","type":"post","link":"https:\/\/www.ecinews.fr\/fr\/fpga-soc-a-architecture-risc-v\/","title":{"rendered":"FPGA SoC \u00e0 architecture RISC-V"},"content":{"rendered":"<p>Annonc\u00e9e au cours de&nbsp;la conf\u00e9rence \u00ab&nbsp;RISC-V Summit&nbsp;\u00bb \u00e0 Santa Clara en Californie (\u00c9tats-Unis), la nouvelle architecture de circuit SoC PolarFire apporte aux plateformes Linux la capacit\u00e9 de multitraitement asym\u00e9trique (AMP) d\u00e9terministe en temps r\u00e9el, dans un groupe coh\u00e9rent de processeurs centraux multi-c\u0153urs. L\u2019architecture SoC PolarFire, d\u00e9velopp\u00e9e en collaboration avec SiFive, int\u00e8gre un sous-syst\u00e8me m\u00e9moire L2 de 2&nbsp;Mo, qui peut \u00eatre configur\u00e9 comme m\u00e9moire cache, m\u00e9moire bloc-notes ou m\u00e9moire d\u2019acc\u00e8s direct. Les d\u00e9veloppeurs peuvent ainsi mettre en \u0153uvre des applications embarqu\u00e9es d\u00e9terministes en temps r\u00e9el simultan\u00e9ment avec un syst\u00e8me d\u2019exploitation riche, pour un grand nombre d\u2019applications avec des contraintes d&rsquo;espaces et thermiques, sur les syst\u00e8mes IoT collaboratifs en r\u00e9seau.&nbsp;<\/p>\n<p>Dans un nouveau contexte r\u00e9gi par la convergence 5G, l\u2019apprentissage automatique et l\u2019Internet des Objets (IoT), les d\u00e9veloppeurs d\u2019applications embarqu\u00e9es ont plus que jamais besoin de la richesse des syst\u00e8mes&nbsp;d\u2019exploitation bas\u00e9s&nbsp;sur un noyau Linux. Ils doivent respecter les exigences syst\u00e8me d\u00e9terministes dans des environnements de d\u00e9veloppement avec de plus en plus de contraintes d\u2019espaces et thermiques, en consommant le moins d\u2019\u00e9nergie possible, tout en respectant par ailleurs des exigences de s\u00e9curit\u00e9 et de fiabilit\u00e9.<\/p>\n<p>Les portes programmables in situ (FPGA) de type System-on-Chip (SoC) traditionnelles associent du mat\u00e9riel reconfigurable avec un processeur&nbsp;prenant en charge&nbsp;Linux sur une seule puce, offrant aux d\u00e9veloppeurs des composants id\u00e9aux&nbsp;pour la personnalisation des applications, mais par ailleurs consommant trop d\u2019\u00e9nergie, ne pr\u00e9sentant pas de niveaux ad\u00e9quats de s\u00e9curit\u00e9 et fiabilit\u00e9, ou utilisant des architectures processeur on\u00e9reuses ou peu flexibles.<\/p>\n<p>Les circuits SoC PolarFire int\u00e8grent des capacit\u00e9s de d\u00e9bogage compl\u00e8tes, incluant la trace des instructions, 50 points d&rsquo;interruption, des moniteurs&nbsp;configurables \u00e0 ex\u00e9cution passive&nbsp;de&nbsp;bus d\u2019interface AXI&nbsp;(Advanced eXtensible Interface)&nbsp;et des moniteurs de structure FPGA, en plus de l\u2019analyseur logique int\u00e9gr\u00e9 \u00e0 deux canaux de Microchip, SmartDebug.&nbsp;<\/p>\n<p>L\u2019architecture SoC PolarFire int\u00e8gre des fonctionnalit\u00e9s de fiabilit\u00e9 et s\u00e9curit\u00e9, telles que la correction SECDED&nbsp;(Single Error Correction and Double Error Detection)&nbsp;sur toutes les m\u00e9moires, la protection de la m\u00e9moire physique, un processeur cryptographique de s\u00e9curit\u00e9 avec analyse de puissance diff\u00e9rentielle (DPA,&nbsp;Differential Power Analysis), le d\u00e9marrage s\u00e9curis\u00e9 de qualit\u00e9 militaire et une de d\u00e9marrage Flash de 128&nbsp;ko.<\/p>\n<p>L\u2019\u00e9valuation et la conception avec une puce-syst\u00e8me PolarFire est compatible avec la plateforme de mod\u00e9lisation de syst\u00e8mes antmicro Renode, qui est d\u00e9sormais int\u00e9gr\u00e9e \u00e0 l&rsquo;environnement de d\u00e9veloppement (IDE) SoftConsole de Microchip pour les syst\u00e8mes embarqu\u00e9s ciblant des SoC PolarFire. Un kit de d\u00e9veloppement SoC PolarFire est \u00e9galement disponible d\u00e8s \u00e0 pr\u00e9sent, compos\u00e9 de la carte d\u2019extension HiFiVe Unleashed, compatible avec les FPGA PolarFire, et la carte de d\u00e9veloppement HiFive Unleashed de SiFive, avec son sous-syst\u00e8me de microprocesseur RISC-V.<\/p>\n<p>Avec&nbsp;cette&nbsp;annonce, Microchip lance&nbsp;son&nbsp;nouveau programme \u00ab&nbsp;Mi-V Embedded Experts&nbsp;\u00bb, un r\u00e9seau de partenariat international destin\u00e9 \u00e0 aider les clients \u00e0 mettre en \u0153uvre leurs syst\u00e8mes mat\u00e9riels\/logiciels int\u00e9grant des SoC PolarFire. Ce programme garantit un support technique pendant tout le cycle de vie des produits du client et permet d\u2019acc\u00e9l\u00e9rer la conception des syst\u00e8mes tout comme leur commercialisation. Les membres du programme peuvent \u00e9galement acc\u00e9der \u00e0 un support technique direct et avoir un acc\u00e8s privil\u00e9gi\u00e9 aux nouvelles plateformes de d\u00e9veloppement&nbsp;et aux nouveaux composants.&nbsp;<\/p>\n<p><a href=\"http:\/\/www.microsemi.com\/polarfiresoc\">www.microsemi.com\/polarfiresoc<\/a><\/p>\n<h3 class=\"title\"><a href=\"http:\/\/www.electronique-eci.com\/Learning-center\/les-processeurs-embarquant-des-blocs-de-propriete-intellectuelle-pour-fpga\">Les processeurs embarquant des blocs de propri\u00e9t\u00e9 intellectuelle pour FPGA permettent l\u2019optimisation du code HDL<\/a><\/h3>\n<h3 class=\"title\"><a href=\"http:\/\/www.electronique-eci.com\/news\/ethernet-audio-et-video-sur-un-seul-cable\">Ethernet, audio et vid\u00e9o sur un seul c\u00e2ble<\/a><\/h3>\n<h3 class=\"title\"><a href=\"http:\/\/www.electronique-eci.com\/news\/la-technologie-inicnet-simplifie-la-creation-de-reseaux-dinfo-loisirs-automobiles\">La technologie INICnet simplifie la cr\u00e9ation de r\u00e9seaux d\u2019info-loisirs automobiles<\/a><\/h3>\n","protected":false},"excerpt":{"rendered":"<p>Microchip, par l\u2019interm\u00e9diaire de sa filiale Microsemi Corporation, annonce l\u2019expansion de son \u00e9cosyst\u00e8me Mi-V en d\u00e9voilant l\u2019architecture d\u2019une nouvelle classe de FPGA SoC. La nouvelle famille associe la famille de FPGA PolarFire milieu de gamme, affichant la plus faible consommation du march\u00e9, avec un sous-syst\u00e8me microprocesseur complet, bas\u00e9 sur l\u2019architecture ISA RISC-V, ouverte et libre de redevances.<\/p>\n","protected":false},"author":9,"featured_media":100621,"comment_status":"closed","ping_status":"closed","sticky":false,"template":"","format":"standard","meta":{"_acf_changed":false,"footnotes":""},"categories":[881],"tags":[],"domains":[47],"ppma_author":[1141],"class_list":["post-100620","post","type-post","status-publish","format-standard","has-post-thumbnail","hentry","category-nouveaux-produits","domains-electronique-eci"],"acf":[],"yoast_head":"<title>FPGA SoC \u00e0 architecture RISC-V ...<\/title>\n<meta name=\"description\" content=\"Microchip, par l\u2019interm\u00e9diaire de sa filiale Microsemi Corporation, annonce l\u2019expansion de son \u00e9cosyst\u00e8me Mi-V en d\u00e9voilant l\u2019architecture d\u2019une...\" \/>\n<meta name=\"robots\" content=\"index, follow, max-snippet:-1, max-image-preview:large, max-video-preview:-1\" \/>\n<link rel=\"canonical\" href=\"https:\/\/www.ecinews.fr\/fr\/wp-json\/wp\/v2\/posts\/100620\/\" \/>\n<meta property=\"og:locale\" content=\"fr_FR\" \/>\n<meta property=\"og:type\" content=\"article\" \/>\n<meta property=\"og:title\" content=\"FPGA SoC \u00e0 architecture RISC-V\" \/>\n<meta property=\"og:description\" content=\"Microchip, par l\u2019interm\u00e9diaire de sa filiale Microsemi Corporation, annonce l\u2019expansion de son \u00e9cosyst\u00e8me Mi-V en d\u00e9voilant l\u2019architecture d\u2019une nouvelle classe de FPGA SoC. La nouvelle famille associe la famille de FPGA PolarFire milieu de gamme, affichant la plus faible consommation du march\u00e9, avec un sous-syst\u00e8me microprocesseur complet, bas\u00e9 sur l\u2019architecture ISA RISC-V, ouverte et libre de redevances.\" \/>\n<meta property=\"og:url\" content=\"https:\/\/www.ecinews.fr\/fr\/wp-json\/wp\/v2\/posts\/100620\/\" \/>\n<meta property=\"og:site_name\" content=\"EENewsEurope\" \/>\n<meta property=\"article:published_time\" content=\"2018-12-10T23:00:44+00:00\" \/>\n<meta property=\"og:image\" content=\"https:\/\/www.ecinews.fr\/wp-content\/uploads\/import\/default\/files\/sites\/default\/files\/images\/eci6767_microchip.jpg\" \/>\n\t<meta property=\"og:image:width\" content=\"1723\" \/>\n\t<meta property=\"og:image:height\" content=\"1150\" \/>\n\t<meta property=\"og:image:type\" content=\"image\/jpeg\" \/>\n<meta name=\"author\" content=\"Alain Dieul\" \/>\n<meta name=\"twitter:card\" content=\"summary_large_image\" \/>\n<meta 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