{"version":"1.0","provider_name":"EENewsEurope","provider_url":"https:\/\/www.ecinews.fr\/fr\/","author_name":"Alain Dieul","author_url":"https:\/\/www.ecinews.fr\/fr\/author\/alaindieul\/","title":"Logiciel de conception de FPGA am\u00e9lior\u00e9","type":"rich","width":600,"height":338,"html":"<blockquote class=\"wp-embedded-content\" data-secret=\"SqdB09u2g7\"><a href=\"https:\/\/www.ecinews.fr\/fr\/logiciel-de-conception-de-fpga-ameliore\/\">Logiciel de conception de FPGA am\u00e9lior\u00e9<\/a><\/blockquote><iframe sandbox=\"allow-scripts\" security=\"restricted\" src=\"https:\/\/www.ecinews.fr\/fr\/logiciel-de-conception-de-fpga-ameliore\/embed\/#?secret=SqdB09u2g7\" width=\"600\" height=\"338\" title=\"\u00ab\u00a0Logiciel de conception de FPGA am\u00e9lior\u00e9\u00a0\u00bb &#8212; EENewsEurope\" data-secret=\"SqdB09u2g7\" frameborder=\"0\" marginwidth=\"0\" marginheight=\"0\" scrolling=\"no\" class=\"wp-embedded-content\"><\/iframe><script type=\"text\/javascript\">\n\/* <![CDATA[ *\/\n\/*! This file is auto-generated *\/\n!function(d,l){\"use strict\";l.querySelector&&d.addEventListener&&\"undefined\"!=typeof URL&&(d.wp=d.wp||{},d.wp.receiveEmbedMessage||(d.wp.receiveEmbedMessage=function(e){var t=e.data;if((t||t.secret||t.message||t.value)&&!\/[^a-zA-Z0-9]\/.test(t.secret)){for(var s,r,n,a=l.querySelectorAll('iframe[data-secret=\"'+t.secret+'\"]'),o=l.querySelectorAll('blockquote[data-secret=\"'+t.secret+'\"]'),c=new RegExp(\"^https?:$\",\"i\"),i=0;i<o.length;i++)o[i].style.display=\"none\";for(i=0;i<a.length;i++)s=a[i],e.source===s.contentWindow&&(s.removeAttribute(\"style\"),\"height\"===t.message?(1e3<(r=parseInt(t.value,10))?r=1e3:~~r<200&&(r=200),s.height=r):\"link\"===t.message&&(r=new URL(s.getAttribute(\"src\")),n=new URL(t.value),c.test(n.protocol))&&n.host===r.host&&l.activeElement===s&&(d.top.location.href=t.value))}},d.addEventListener(\"message\",d.wp.receiveEmbedMessage,!1),l.addEventListener(\"DOMContentLoaded\",function(){for(var e,t,s=l.querySelectorAll(\"iframe.wp-embedded-content\"),r=0;r<s.length;r++)(t=(e=s[r]).getAttribute(\"data-secret\"))||(t=Math.random().toString(36).substring(2,12),e.src+=\"#?secret=\"+t,e.setAttribute(\"data-secret\",t)),e.contentWindow.postMessage({message:\"ready\",secret:t},\"*\")},!1)))}(window,document);\n\/* ]]> *\/\n<\/script>\n","thumbnail_url":"https:\/\/www.ecinews.fr\/wp-content\/uploads\/import\/default\/files\/sites\/default\/files\/images\/eci8506_mirosemi_libero_design_flow.png","thumbnail_width":879,"thumbnail_height":502,"description":"R\u00e9unissant une gamme compl\u00e8te d'outils de conception de FPGA, la version 11.8 du logiciel Libero SoC (system-on-chip) de Microsemi comprend des am\u00e9liorations significatives telles que la simulation en langage mixte, de meilleures capacit\u00e9s de d\u00e9bogage et une pr\u00e9sentation revisit\u00e9e de la netlist. En outre, elle est accompagn\u00e9e d\u2019une licence d'\u00e9valuation pour tester les FPGA et SoC propri\u00e9taires bas\u00e9s Flash."}