{"version":"1.0","provider_name":"EENewsEurope","provider_url":"https:\/\/www.ecinews.fr\/fr\/","author_name":"eeNews Europe","author_url":"https:\/\/www.ecinews.fr\/fr\/author\/eenews-europe\/","title":"FPGA \u00e9conomiques et \u00e0 faible consommation","type":"rich","width":600,"height":338,"html":"<blockquote class=\"wp-embedded-content\" data-secret=\"TIEk4v3Zuw\"><a href=\"https:\/\/www.ecinews.fr\/fr\/fpga-economiques-et-a-faible-consommation\/\">FPGA \u00e9conomiques et \u00e0 faible consommation<\/a><\/blockquote><iframe sandbox=\"allow-scripts\" security=\"restricted\" src=\"https:\/\/www.ecinews.fr\/fr\/fpga-economiques-et-a-faible-consommation\/embed\/#?secret=TIEk4v3Zuw\" width=\"600\" height=\"338\" title=\"\u00ab\u00a0FPGA \u00e9conomiques et \u00e0 faible consommation\u00a0\u00bb &#8212; EENewsEurope\" data-secret=\"TIEk4v3Zuw\" frameborder=\"0\" marginwidth=\"0\" marginheight=\"0\" scrolling=\"no\" class=\"wp-embedded-content\"><\/iframe><script type=\"text\/javascript\">\n\/* <![CDATA[ *\/\n\/*! This file is auto-generated *\/\n!function(d,l){\"use strict\";l.querySelector&&d.addEventListener&&\"undefined\"!=typeof URL&&(d.wp=d.wp||{},d.wp.receiveEmbedMessage||(d.wp.receiveEmbedMessage=function(e){var t=e.data;if((t||t.secret||t.message||t.value)&&!\/[^a-zA-Z0-9]\/.test(t.secret)){for(var s,r,n,a=l.querySelectorAll('iframe[data-secret=\"'+t.secret+'\"]'),o=l.querySelectorAll('blockquote[data-secret=\"'+t.secret+'\"]'),c=new RegExp(\"^https?:$\",\"i\"),i=0;i<o.length;i++)o[i].style.display=\"none\";for(i=0;i<a.length;i++)s=a[i],e.source===s.contentWindow&&(s.removeAttribute(\"style\"),\"height\"===t.message?(1e3<(r=parseInt(t.value,10))?r=1e3:~~r<200&&(r=200),s.height=r):\"link\"===t.message&&(r=new URL(s.getAttribute(\"src\")),n=new URL(t.value),c.test(n.protocol))&&n.host===r.host&&l.activeElement===s&&(d.top.location.href=t.value))}},d.addEventListener(\"message\",d.wp.receiveEmbedMessage,!1),l.addEventListener(\"DOMContentLoaded\",function(){for(var e,t,s=l.querySelectorAll(\"iframe.wp-embedded-content\"),r=0;r<s.length;r++)(t=(e=s[r]).getAttribute(\"data-secret\"))||(t=Math.random().toString(36).substring(2,12),e.src+=\"#?secret=\"+t,e.setAttribute(\"data-secret\",t)),e.contentWindow.postMessage({message:\"ready\",secret:t},\"*\")},!1)))}(window,document);\n\/* ]]> *\/\n<\/script>\n","thumbnail_url":"https:\/\/www.ecinews.fr\/wp-content\/uploads\/import\/default\/files\/import\/eci3052_lattice.jpg","thumbnail_width":2100,"thumbnail_height":1500,"description":"Lattice Semiconductor red\u00e9finit le domaine du FPGA milieu de gamme \u00e0 faible co\u00fbt et basse consommation en annon\u00e7ant sa famille FPGA de nouvelle g\u00e9n\u00e9ration, r\u00e9f\u00e9renc\u00e9e LatticeECP4, et dot\u00e9e de SERDES \u00e0 6 Gbits\/s en bo\u00eetiers \u00e9conomiques \" wire-bond \", de puissants blocs DSP et de moteurs de communication bas\u00e9s sur des hard IP. Ces circuits FPGA ciblent les applications sensibles en co\u00fbt et en consommation des march\u00e9s du sans fil, du filaire, de la vid\u00e9o et de l'informatique."}